Conference Proceeding

High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology

Fujitsu Lab. Ltd., Tokyo
01/2008; DOI:10.1109/IEDM.2007.4418915 ISBN: 978-1-4244-1508-3 pp.251 - 254 In proceeding of: Electron Devices Meeting, 2007. IEDM 2007. IEEE International
Source: IEEE Xplore

ABSTRACT We present an aggressively-scaled high-performance and low-power bulk CMOS platform technology aiming at large-scale (multi-core) high-end use with 45-nm ground rule. By utilizing a high-epsilon offset spacer and FET specific multiple-stressors with highly enhanced strain, world competitive high performance NFET and PFET drive currents of 1.22/0.765 mA/mum at 100 nA/mum off-current, and 0.97/0.63 mA/mum at 10 nA/mum off-current at |Vd|= 1V, respectively, were obtained with minimizing layout dependence. This technology also offers a functional high density SRAM with a much smaller cell, i.e., 0.255 mum2. In addition, full- porous low-k (k = 2.25) BEOL integration lowers RC delay and reduces total circuit delay by 25% at the long wiring region compared to that of our previous technology.

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Keywords

10 nA/mum off-current
 
100 nA/mum off-current
 
45-nm ground rule
 
FET specific multiple-stressors
 
layout dependence
 
low-power bulk CMOS platform technology
 
PFET drive currents
 
RC delay
 
smaller cell
 
total circuit delay
 
utilizing