Design approach of newly developed 3.3kV IGBT modules

Abstract

High voltage IGBT (HVIGBT) modules with high performance in the areas of low power loss and high reliability are required for high power applications such as traction, large industrial motor drives, and medium voltage converters. Unfortunately, these performances are often in reciprocal relationship. In order to achieve a higher performance with optimized tradeoffs at the 3.3 kV level, a new IGBT and free wheeling diode (FWD) chip set was developed. This paper describes the optimization of the chip design using several simulation tools and Taguchi method experiments to find the most influential design factors and to secure the most robust design.

Full text

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EPE 2007 Aalborg

Design Approach of Newly Developed 3.3kV IGBT Modules
Shinichi Iura(1), John F. Donlon(2), Eckhard Thal(3)
(1)MITSUBISHI ELECTRIC, POWER DEVICE WORKS
1-1-1 Imajukuhigashi Nishi-ku
Fukuoka, Japan
Tel.: +81 / (92) – 805.3395
Fax: +81 / (92) – 805.3745

(2)POWEREX, INC.
173 Pavilion Lane
Youngwood, PA 15697, USA
Tel.: +1 / (724) – 925.4377
Fax: +1 / (724) – 925.4393

(3)MITSUBISHI ELECTRIC EUROPE B.V.
Gothaer Str. 8, 40880
Ratingen, Germany
Tel.: +49 / (2102) – 486.2850
Fax: +49 / (2102) – 486.7220

E-Mail: Iura.Shinichi@aj.MitsubishiElectric.co.jp
URL: http://Global.MitsubishiElectric.com

Keywords
Device characterisation, Design, Free wheel diode (FWD), IGBT, Power semiconductor device,
Robustness
Abstract
High Voltage IGBT (HVIGBT) modules with high performance in the areas of low power loss and
high reliability are required for high power applications such as traction, large industrial motor drives,
and medium voltage converters. Unfortunately, these performances are often in reciprocal
relationship. In order to achieve a higher performance with optimized tradeoffs at the 3.3kV level, a
new IGBT and Free wheeling Diode (FWD) chip set was developed. This paper describes the
optimization of the chip design using several simulation tools and Taguchi Method experiments to find
the most influential design factors and to secure the most robust design.
Introduction
3.3kV IGBT modules are used in high power inverter applications where low loss and fault tolerance
are key considerations. For the IGBT chip this means low on-state conduction loss without sacrifice
of switching and short circuit Safe Operating Area (SOA). For the FWD chip this means strong
forward surge current and I2t capability. Simulation and experimental investigation were combined to
develop new IGBT and FWD chips that meet these requirements for a more robust 3.3kV IGBT
module.

The following sections will describe the design approach focusing on overload performance for
illustrative purposes.

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EPE 2007 Aalborg

IGBT chip design
The newly developed 3.3kV IGBT chip improved the tradeoff characteristic between on-state voltage
and turn-off switching energy by 25% compared to the conventional design as shown in Fig. 1. [1]
However, an IGBT has tradeoffs as shown in Fig. 2. Therefore higher performance in on-state voltage
and turn-off switching energy without loss of safe operating area robustness is the key consideration
for device design improvement. [2]

1000
1400
1800
2200
2600
3000
22.533.54
VCE(sat) [V]
Eoff [mJ/P]
ConventionalNew

0
20
40
60
80
100
RBSOA
01234


Fig. 1: VCE(sat) vs. Eoff tradeoff curve
Tj=125°C, nominal conditions

The conventional design approach had wide margin to secure SOA while sacrificing electrical
performance. For example, short circuit SOA has the relationship between short circuit current and
gate threshold voltage (VGE(th)) shown in Fig. 3. Wide design margin was needed to satisfy short
circuit capability under the highest current conditions, i.e., minimum VGE(th), allowing for wide
tolerance. In order to improve the tradeoffs in Fig. 2, the possibility of reducing the VGE(th) variance
was verified by Taguchi method experiments. [3]

Fig. 2: Design tradeoffs for IGBTs
5000
6000
7000
8000
9000
10000
11000
55.566.57
VGE(th) [V]
Short circuit current [A]


Fig. 3: VGE(th) vs. Short circuit current
VGE(th) at Tj=25°C, VCE=10V, IC=1/10000 × nominal current
Short circuit current at Tj=125°C, Vcc=2500V, VGE=±15V

Between the average value and standard deviation, it is typically easy to adjust the average value to a
specific target, but reducing the variance is difficult. Therefore, an experiment was carried out using
Taguchi Methods to achieve both of the following two areas [4]:
· Minimizing design variance
· Adjusting the average value on target.
Eoff
VCE(sat)
SCSOA

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EPE 2007 Aalborg

Optimization of the IGBT chip was accomplished by investigating the effects of variations of the
IGBT chip design parameters on the VGE(th) characteristic. Fig. 4 shows the location of five chip
design parameters (A to E) that were considered to have an effect on VGE(th). Modifications to the ion
injection doping conditions were the main variations used for these parameters. The variations of
parameter A were put on 2 levels and parameters B to E were put on 3 levels as shown in Table I.
Table II shows the matrix of experimental factors for the five design parameters based on L18
orthogonal table. Sample numbers (n) are 36 chips (18 tests times 2). The experimental results were
analyzed by Taguchi Methods to identify the most influential factors.


(A), (B) (C) (E) (A), (B) (C) (E)
Design parameters
N+bufferN+bufferN+buffer
P-collectorP-collectorP-collector
P+ P+P+
CDCDCD
NWNWNW
MOSFET cellMOSFET cellMOSFET cell
J-FET
region regionregion
J-FET
regionregionregion
(D) (D)
J-FETJ-FETJ-FETJ-FET

(A) : P- channel dope pattern width
(B) : P- channel dope concentration
(C) : n+ JFET implant concentration
(D) : P-collector concentration
(E) : P+ contact concentration


Fig. 4: Cross-sectional view of an IGBT chip indicating design parameter locations


Table I: Experimental factors for the five design parameters
#
Design parameters Level 1 Level 2 Level 3
A P- channel dope pattern width standard narrow -
B P- channel dope concentration
×0.8 standard
standard
×1.2 standard
C n+ JFET implant concentration standard
×1.5 standard
×2.0 standard
D P- collector concentration
×1/3 standard
×1/2 standard
standard
E P+ contact concentration standard
×2.0 standard
×3.0 standard

Table II: Matrix table for the five parameters based on L18 orthogonal table
NoABCDENoA
standard
standard
standard
standard
standard
standard
standard
standard
standard
nallow
nallow
nallow
nallow
nallow
nallow
nallow
nallow
nallow
BC
standard
x2.0 standard
x1.5 standard
standard
x2.0 standard
x1.5 standard
standard
x2.0 standard
x1.5 standard
standard
x2.0 standard
x1.5 standard
standard
x2.0 standard
x1.5 standard
standard
x2.0 standard
x1.5 standard
DE
standard1
2
3
4
5
6
7
8
9
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
1
1
1
2
2
2
3
3
3
1
1
1
2
2
2
3
3
3
1
3
2
1
3
2
1
3
2
1
3
2
1
3
2
1
3
2
1
2
3
1
2
3
2
3
1
3
1
2
2
3
1
3
1
2
1
2
3
2
3
1
1
2
3
3
1
2
3
1
2
2
3
1
1
2
3
4
5
6
7
8
9
x0.8 standard
x0.8 standard
x0.8 standard
standard
standard
standard
x1.2 standard
x1.2 standard
x1.2 standard
x0.8 standard
x0.8 standard
x0.8 standard
standard
standard
standard
x1.2 standard
x1.2 standard
x1.2 standard
x1/3 standard
x1/2 standard
standard
x1/3 standard
x1/2 standard
standard
x1/2 standard
standard
x1/3 standard
standard
x1/3 standard
x1/2 standard
x1/2 standard
standard
x1/3 standard
standard
x1/3 standard
x1/2 standard
x2.0 standard
x3.0 standard
x2.0 standard
x3.0 standard
standard
standard
x2.0 standard
x3.0 standard
x3.0 standard
standard
x2.0 standard
x3.0 standard
standard
x2.0 standard
x2.0 standard
x3.0 standard
standard
10
11
12
13
14
15
16
17
18
10
11
12
13
14
15
16
17
18
Experimental design parametersL18 orthogonal table for 5 parameters

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EPE 2007 Aalborg

Minimizing variance design
The signal to noise (S/N) ratio is an ideal criterion for minimizing variance where the higher S/N ratio
denotes less variance. The S/N ratio is given by the following equation:
()
em
V
σ
e
nVS
log
m
logN/S
−
==
10 10
2
2
where
()
n
y
Sm
2
∑
=
,
()
1
2
−
−∑
=
n
yy
Ve
(1)
Table III shows the experiment results. Multiple regression analysis is applied to the data in Table III
to produce the S/N ratio and average values for each level for each parameter. Fig. 5 illustrates with
bar graphs the difference between the maximum and minimum S/N ratio in Table IV. A bigger
difference means a stronger influential factor. From this result, it is seen that parameters C and E are
the most influential factors on the variance of the VGE(th) characteristic.

Table III: Experiment results of VGE(th) at Tj=25°C, VCE=10V, IC(nominal) × × 1/10000
SmVeS/N ratioAverage
No y1y2
1
2
3
4
5
6
7
8
9
5.76
5.00
5.40
6.58
6.18
6.16
7.24
6.78
6.76
6.66
6.48
6.44
7.50
7.32
7.30
8.30
8.06
8.06
5.76
4.99
5.36
6.58
6.14
6.16
7.22
6.74
6.80
6.68
6.50
6.44
7.52
7.34
7.34
8.30
8.08
8.04
66.34
49.93
57.89
86.58
75.89
75.88
104.55
91.40
91.94
88.98
84.24
82.93
112.80
107.46
107.16
137.76
130.25
129.61
5.0E-07
2.4E-05
8.0E-04
5.0E-07
8.0E-04
5.0E-07
2.0E-04
8.0E-04
8.0E-04
2.0E-04
2.0E-04
5.0E-07
2.0E-04
2.0E-04
8.0E-04
5.0E-07
2.0E-04
2.0E-04
78.22
60.26
45.58
79.37
46.76
78.80
54.17
47.57
47.59
53.47
53.23
79.19
54.50
54.29
48.26
81.39
55.13
55.11
5.76
5.00
5.38
6.58
6.16
6.16
7.23
6.76
6.78
6.67
6.49
6.44
7.51
7.33
7.32
8.30
8.07
8.05
10
11
12
13
14
15
16
17
18
VGE(th) [V]


Table IV: Multiple regression analysis results of S/N ratio for each design parameter
ABCDE
Level 1
Level 2
Level 3
Level 1
Level 2
Level 3
59.81 61.66 66.86 60.30 62.30
59.40 60.33 59.09 58.33 66.01
-56.83 52.87 60.18 50.51
6.20
5.967.01
7.356.846.63
-7.536.69
6.83
6.73
6.77
6.84
6.73
6.76
S/N ratio
Average
Yellow cells : highest S/N ratio
Blue cells : lowest S/N ratio
0
2
4
6
8
10
12
14
16
18
ABCDE
Design parameters
S/N ratio difference between
(max - min)


Fig. 5: Influential factors for S/N ratio of
VGE(th)

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EPE 2007 Aalborg

Table V then shows the comparison of gain between the original design and an optimized design based
on optimizing parameters B, D, and E. The result is a gain of 5.15db. The improved ratio can be
found by the following equation:

2
10
σ
()
optimized
σ

11
22
.
.
()
()
optimized
dardtans
logGain
2
σ
=

()
10
2
2
Gain
log
dardtans
=
σ

(2)
()
553
.
001
273
10
10
)dardtans(
Gain
optimized
=×=σ×=σ

(3)
Thus, variance can be improved by 1/3.3 and the standard deviation reduced by 45% (see Fig. 6).

Table V: Gain between the standard design and the optimized design where the
red marked cells are optimized conditions for highest S/N ratio
Parameters Level 1 Level 2 Level 3 Standard
(S/N ratio)
Optimized
(S/N ratio)
A standard narrow - 0.00
(59.81)
0.00
(60.33)
0.00
(66.86)
0.00
(60.18)
0.00
(62.31)
Gain
0.00
(?)
1.33
(61.66)
0.00
(?)
0.12
(60.30)
3.70
(66.01)
5.15 db
B
×0.8 standard
standard
×1.2 standard

C standard
×1.5 standard
×2.0 standard

D
×1/3 standard
×1/2 standard
standard
E standard
×2.0 standard
×3.0 standard



05
VGE(th) [V]
10
Frequency
Standard conditions
Optimized conditions

Fig. 6: Expected distribution of VGE(th) by optimized design on highest S/N ratio

Adjusting the average value on target
Fig. 7 also shows the multiple regression analysis applied to the average value. From this result, the
average value can be best adjusted by parameter A or B. For adjusting the average value, it is
necessary to consider the factors that have a lower influence in Fig. 5 but a higher influence in Fig. 7
to achieve an improved distribution.