Conference Proceeding

A 2.5-Gb/s 0.13-μm CMOS current mode logic transceiver with pre-emphasis and equalization

Nat. Univ. of Defense Technol., Changsha;
11/2007; DOI:10.1109/ICASIC.2007.4415643 ISBN: 978-1-4244-1132-0 pp.368 - 371 In proceeding of: ASIC, 2007. ASICON '07. 7th International Conference on
Source: IEEE Xplore

ABSTRACT A 2.5-Gb/s current-mode logic (CML) transceiver is implemented in 0.13 - mum CMOS technology for serial inter-chip interconnection. To compensate the channel attenuation and other impairments, pre-emphasis circuit is included at the transmitter and equalizer at the receiver. 6-GHz 3 dB bandwidth is achieved through the use of active inductors instead of online spiral inductors. DC offset compensate circuits are employed in the output and input buffers to keep the common mode voltage stable. Layout simulation demonstrates the effectiveness of the transceiver. This transceiver consumes only 160 mw of power with 2.5v power supply. The die area of transmitter and receiver are 0.015 mm2, 0.01 mm2 respectively. The transceiver can be operated at 2.5-Gb/s with 100 mv receiver sensitivity.

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Keywords

100 mv receiver sensitivity
 
6-GHz 3 dB bandwidth
 
active inductors
 
channel attenuation
 
circuits
 
common mode voltage stable
 
DC
 
impairments
 
input buffers
 
mum CMOS technology
 
online spiral inductors
 
pre-emphasis circuit
 
serial inter-chip interconnection
 
transceiver
 
transceiver consumes
 

Zhenyu Zhao