Conference Paper

Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip

DOI: 10.1109/RTSS.2007.24 Conference: Real-Time Systems Symposium, 2007. RTSS 2007. 28th IEEE International
Source: IEEE Xplore

ABSTRACT In multiprocessor systems, the traffic on the bus does not solely originate from data transfers due to data dependen- cies between tasks, but is also affected by memory trans- fers as result of cache misses. This has a huge impact on worst-case execution time (WCET) analysis and, in general, on the predictability of real-time applications implemented on such systems. As opposed to the WCET analysis per- formed for a single processor system, where the cache miss penalty is considered constant, in a multiprocessor system each cache miss has a variable penalty, depending on the bus contention. This affects the tasks' WCET which, how- ever, is needed in order to perform system scheduling. At the same time, the WCET depends on the system schedule due to the bus interference. In this paper we present an approach to worst-case execution time analysis and system scheduling for real-time applications implemented on mul- tiprocessor SoC architectures. The emphasis of this paper is on the bus scheduling policy and its optimization, which is of huge importance for the performance of such a pre- dictable multiprocessor application.

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