Conference Paper

A Real-Time Feedback Controlled Hearing Aid Chip with Reference Ear Model

Korea Adv. Inst. of Sci. & Technol., Daejeon
DOI: 10.1109/CICC.2007.4405696 Conference: Custom Integrated Circuits Conference, 2007. CICC '07. IEEE
Source: IEEE Xplore


A real-time hearing aid chip with the reference ear model (REM) and the comparison processor (COMP) is proposed and implemented. Through the COMP the response differences between the reference ear model and the impaired ear of the patient are achieved and processed to compensate the hearing loss of the patient. By adopting this architecture, the fully internal gain fitting and verification of the hearing aid with only single initial hearing loss test is implemented. To reduce the power dissipation and achieve the high flexibility, the preamplifier which has programmable multi threshold voltages is introduced. The feedback controlled hearing aid chip is implemented in 0.18 mum CMOS technology, consumes less than 110 muW and has a die size of 3.7 mm2.

9 Reads
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: A low-power digital hearing aid chip with consideration of the human external ear characteristics according to the each individual user is proposed and implemented. It adopts the pre fitting verification algorithm (PREVA) to obtain the fast and accurate gain fitting and verification in two steps, coarse and fine gain fittings. The ear canal modeling filter circuit (EMC) which models the human external ear into the distributed LC filter enables the coarse gain fitting based on the shape of the external ear of the patient. The fine fitting verification is performed by the external inputs from the hearing loss test results. To reduce the power consumption of the human factored hearing aid chip design, the multi-threshold preamplifier, the adaptive fitting digital signal processor (DSP) with the filter reuse technique and the gated successive approximation ADC are designed and embedded to the digital hearing aid chip. The dynamic range of the multi-threshold preamplifier exists from 0.45 V to 0.8 V and dissipates 32 muW from a single 0.9 V supply. The fabricated digital hearing aid chip achieves the peak SNR of 81 dB in the overall system with 4.2 muV of input-referred noise voltage. The fabricated chip occupies the core area of 3.12times1.20 mm<sup>2</sup> in a 0.18 mum standard CMOS technology and consumes only 107 muW from a single 0.9 V supply.
    IEEE Journal of Solid-State Circuits 02/2008; 43(1-43):266 - 274. DOI:10.1109/JSSC.2007.914721 · 3.01 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: A low-power, energy-efficient analog front-end circuit is proposed and implemented for a digital hearing aid chip. It adopts the combined-gain-control (CGC) technique for an accurate preamplification and the adaptive-SNR (ASNR) technique for an improvement of dynamic range with low power consumption. The proposed analog front-end achieves 87-dB peak SNR and dissipates 60-μW from a single 0.9-V supply. The core area is 0.5-mm<sup>2</sup> in a 0.25-μm standard CMOS technology.
    VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents a digital signal processing IC, including AD/DA converters, for one-chip hearing instruments. An on-chip infrared remote control receiver is used to load a program Into the digital signal processor (DSP). The complete IC consumes 2 mW from a single cell battery and operates with supply voltages down to 0.9 V. The oversampling A/D and D/A converters show a dynamic range of 77 and 93 dBA, respectively. Only a few external capacitors are needed. The chip area is 35 mm<sup>2</sup> in a low-threshold 0.8-μm CMOS process
    IEEE Journal of Solid-State Circuits 12/1997; 32(11-32):1790 - 1806. DOI:10.1109/4.641702 · 3.01 Impact Factor


9 Reads
Available from