Conference Proceeding

Test Scheduling for Memory Cores with Built-In Self-Repair

Nara Inst. of Sci. & Technol., Kansai Science City;
11/2007; DOI:10.1109/ATS.2007.26 ISBN: 978-0-7695-2890-8 pp.199-206 In proceeding of: Asian Test Symposium, 2007. ATS '07. 16th
Source: IEEE Xplore

ABSTRACT This paper presents a stage-based test scheduling for memory cores with BISR scheme under power constraint. We introduce a model to compute the expected test time for a given test schedule for memory cores with BISR scheme based on pass probabilities, and propose a test scheduling algorithm to minimize the expected test time. Experimental results show a significant expected test time reduction compared to the core-based test scheduling method which minimizes the test time.

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Keywords

BISR scheme
 
core-based test scheduling method
 
expected test time
 
Experimental results
 
given test schedule
 
memory cores
 
power constraint
 
probabilities
 
stage-based test scheduling
 
test scheduling algorithm
 
test time
 
test time reduction