Conference Paper

An HDL-Based Platform for High Level NoC Switch Testing

Univ. of Tehran, Tehran
DOI: 10.1109/ATS.2007.97 Conference: Asian Test Symposium, 2007. ATS '07. 16th
Source: IEEE Xplore


This paper presents a non-scan method of NoC switch testing. The method requires addition of test-mode hardware for NoC switches and processing elements which is much less than what is required for most scan methods. Associated with our proposed test-mode of an NoC, we have developed a test environment based on high-level switch faults. The test environment applies test packets to the NoC-under-test in its test-mode and generates an NoC fault dictionary to be used for error detection of an NoC running in the test-mode. Proposed fault models and test strategy will be discussed in this paper.

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    ABSTRACT: A test strategy for testing NoC switches based on flooding is presented in this paper. This test strategy tests all switch ports and network routes, while it avoids sending a test packet arriving at a switch in every direction. This test strategy is referred to as pseudo-exhaustive, versus the exhaustive testing that sends an incoming test packet of a switch in every direction. As compared with the exhaustive strategy, the pseudo- exhaustive testing consumes lower power consumption, has a lower test time and still has 100% switch port fault coverage. This paper discusses our test strategy, test mode switch hardware requirements, and evaluates test power, time, and coverage.
    VLSI Design, 2008. VLSID 2008. 21st International Conference on; 02/2008
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    ABSTRACT: An exhaustive test strategy based on flooding routing for NoC switches is presented in this paper. Some test-mode hardware is added to the switches to enable them to multicast their incoming packets thus examining all existing routes in the network. A test environment based on high-level switch faults is used which injects high level routing faults into the NoC-Under-Test and considers the total number of the packets received at the destination for fault detection. Experimental results show that that 100% fault coverage can be achieved with a small amount of test hardware overhead within an acceptable test time.
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    ABSTRACT: This paper presents an efficient method for online testing of NoC switches. This method deals with control faults of NoC switches; i.e. the routing faults which cause NoC packets to be sent to output ports not intended to. A high level fault model has been proposed in this paper to model switch routing faults. The proposed method is evaluated by fault simulation that is based on our high-level fault model. This simulation and evaluation environment is modeled at the transaction level in VHDL.
    Defect and Fault-Tolerance in VLSI Systems, 2007. DFT '07. 22nd IEEE International Symposium on; 10/2007
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