An HDL-Based Platform for High Level NoC Switch Testing
ABSTRACT This paper presents a non-scan method of NoC switch testing. The method requires addition of test-mode hardware for NoC switches and processing elements which is much less than what is required for most scan methods. Associated with our proposed test-mode of an NoC, we have developed a test environment based on high-level switch faults. The test environment applies test packets to the NoC-under-test in its test-mode and generates an NoC fault dictionary to be used for error detection of an NoC running in the test-mode. Proposed fault models and test strategy will be discussed in this paper.
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Conference Paper: Functional Testing Approaches for BIFST-able tlm_fifo[Show abstract] [Hide abstract]
ABSTRACT: Evolution of Electronic System Level design methodologies, allows a wider use of Transaction-Level Modeling (TLM). TLM is a high-level approach to modeling digital systems that emphasizes on separating communications among modules from the details of functional units. This paper explores different functional testing approaches for the implementation of Built-in Functional Self Test facilities in the TLM primitive channel tlm_fifo. In particular, it focuses on three different test approaches based on a finite state machine model of tlm_fifo, functional fault models, and march tests respectively.IEEE International High Level Design Validation and Test Workshop (HLDVT); 11/2008
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ABSTRACT: On the basis of the study in Network on Chip (NoC) topologies, routing algorithm, data exchange and virtual channel technology, we design an online detection method of interconnection for 2D torus structure of NoC system in this paper. This method can detect the data errors during transmission, and identify the error results from the routing switch failure or the data transmission interconnection line failure. Then we design a sub-router based on the wormhole exchange using E-cube routing algorithm, and a check module which is suitable for the original routing node functions and work feature. Finally, we simulate the method by Verilog HDL and quartus II software. The experiment results show that the method can detect data errors caused by the router failure or interconnect failure and can locate the fault.01/2011;
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ABSTRACT: Reliability in embedded systems is crucial for many application domains. Especially, for safety critical application, as they can be found in the automotive and avionic domain, a high reliability has to be ensured. The technology in chip production undergoes a steady shrinking process from nowadays 25 nanometers. It is proven that coming technologies, which are much smaller, can have a higher defect rate after production, but also at runtime. The physical effects at runtime come from a higher susceptibility for radiation. Since the silicon die of a field programmable gate array (FPGA) includes a high amount of physical wiring, the radiation effect plays here a major role. Therefore, this article describes an approach of a reliable Network-on-Chip (NoC) which can be used for an FPGA-based system. The article describes the concept and the physical realization of this NoC and evaluates its reliability.ACM Transactions on Embedded Computing Systems (TECS). 03/2013; 12(1s).