Conference Paper

Integrated Inductors in HR SOI CMOS technologies: on the economic advantage of SOI technologies for the integration of RF applications

STMicroelectron., Crolles
DOI: 10.1109/SOI.2007.4357881 Conference: SOI Conference, 2007 IEEE International
Source: IEEE Xplore

ABSTRACT This paper presents high-Q and high-inductance-density on-chip inductors made on high resistivity (HR) substrate using STMicroelectronics LP 65 nm SOI CMOS technology with 6 copper metal layers. For the first time, on-chip inductor architectures dedicated to HR SOI CMOS technology are reported and benchmarked with current one used in standard RF CMOS technologies. According to the measurement results, proposed 3D HR SOI inductor occupies only 50% of the area of the conventional planar spiral inductor with the same inductance and similar quality factor. By virtue of the small area consumed by those 3D inductors, the size and cost of the radio frequency (RF) chip integrated on HR SOI can be significantly reduced in comparison with standard bulk technology which reenforces the advantage of SOI technology for RF applications.

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