Power Management of Multicore Multiple Voltage Embedded Systems by Task Scheduling
ABSTRACT We study the role of task-level scheduling in power management on multicore multiple voltage embedded systems. Multicore on-a- chip, in particular DSP systems, can greatly improve performance through parallelism. On the other hand, dynamic voltage scaling (DVS) has been shown to be one of the most effective low power design techniques and multiple supply voltage system is among the most practical and well-studied DVS systems. The integration of multiple cores/processors on a chip naturally makes the system suitable for DVS with new innovations such as voltage island. In this paper, we discuss how to reduce multicore system's power consumption by utilizing multiple supply voltages. We first formulate the power management problem for multicore multi-voltage embedded systems and show that the problem is NP-hard, but the NP- hardness can be removed for several real life applications. More specific, we develop polynomial algorithms to find the optimal solutions for two special cases. The first case is when preemption is allowed, and the second one is when the system uses the first-come - first-serve (FCFS) service strategy. We prove both algorithms' optimality and analyze their run-time complexity. Simulation on real- life and randomly generated tasks show that the optimal preemption scheduler provides significant energy saving. Our goal in this paper is to build a solid foundation for the power management problem on multicore multiple voltage systems and to study real life applications where the problem can be solved optimally.
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ABSTRACT: In recent years, applications like multimedia, video and audio stream communications, 3D movies, to name a few, have spurred the proliferation of multiprocessor systems, particularly for real-time embedded systems. However, the complex architecture and heavy computing demands of such systems increase power consumption. Therefore, energy conservation has become a critical issue. In this paper, we propose a novel tasks scheduling algorithm for real-time multiprocessor systems. The algorithm works by reducing the workload in high speed processors with the aid of task migration so that the entire system can switch to low speed/low voltage as soon as it can reduce power consumption. The overhead of transitioning to low voltage is also analyzed and used as a criterion to determine whether the transition is beneficial. The effect of important parameters such as task granularity on the performance is also investigated, and simulation results based on realistic processor power consumption models are shown to be promising.The Journal of Supercomputing 11/2012; 62(2). · 0.92 Impact Factor
Conference Paper: Multi-core fixed priority DVS scheduling[Show abstract] [Hide abstract]
ABSTRACT: In this paper, we study offline and online DVS algorithms for Fixed Priority tasks scheduled on multi-core systems. The offline multi-core algorithm (MC-SSS) slows down tasks with a static slowdown speed based on multi-core fixed priority schedulability analysis. And the on-line algorithm (MC-ccFPP) combines load balancing algorithm and cycle conservative slack analysis to slow down tasks. Experimental results for random tasks set are shown and the analysis of the experimental results is provided. Performance analysis studies the energy saving for the offline multi-core algorithm (MC-SSS) and the online multi-core algorithm (MC-ccFPP) for a variety of task sets with different CPU utilization, different number of tasks and different number of cores.Proceedings of the 12th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I; 09/2012
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ABSTRACT: We present a novel and highly automated technique for dynamic system level power management of System-on-a-Chip (SoC) designs. We present a formal system to represent power constraints and power intent as rules. We also present a Term Rewriting Systems based rule rewriting engine as our dynamic power manager. We provide a notion of formal correctness of our rule engine execution and provide a robust algorithm to dynamically and automatically manage power consumption in large SoC designs. There are two fundamental building blocks at the core of our technique. First, we present a powerful formal system to capture power constraints and power intent as rules. This is a self-checking system and will automatically flag conflicting constraints or rules. Next, we present a rewriting strategy for managing power constraint rules using a formal deductive logic technique specially honed for dynamic power management of SoC designs. Together, this provides a common platform and representation to seamlessly cooperate between hardware and software constraints to achieve maximum platform power optimization dynamically during execution. We demonstrate our technique in multiple contexts on an SoC design of the state-of-the-art next generation Intel smartphone platform.Quality Electronic Design (ISQED), 2013 14th International Symposium on; 01/2013