Conference Paper

Power Management of Multicore Multiple Voltage Embedded Systems by Task Scheduling

Univ. of Maryland, College Park
DOI: 10.1109/ICPPW.2007.69 Conference: Parallel Processing Workshops, 2007. ICPPW 2007. International Conference on
Source: IEEE Xplore


We study the role of task-level scheduling in power management on multicore multiple voltage embedded systems. Multicore on-a- chip, in particular DSP systems, can greatly improve performance through parallelism. On the other hand, dynamic voltage scaling (DVS) has been shown to be one of the most effective low power design techniques and multiple supply voltage system is among the most practical and well-studied DVS systems. The integration of multiple cores/processors on a chip naturally makes the system suitable for DVS with new innovations such as voltage island. In this paper, we discuss how to reduce multicore system's power consumption by utilizing multiple supply voltages. We first formulate the power management problem for multicore multi-voltage embedded systems and show that the problem is NP-hard, but the NP- hardness can be removed for several real life applications. More specific, we develop polynomial algorithms to find the optimal solutions for two special cases. The first case is when preemption is allowed, and the second one is when the system uses the first-come - first-serve (FCFS) service strategy. We prove both algorithms' optimality and analyze their run-time complexity. Simulation on real- life and randomly generated tasks show that the optimal preemption scheduler provides significant energy saving. Our goal in this paper is to build a solid foundation for the power management problem on multicore multiple voltage systems and to study real life applications where the problem can be solved optimally.

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    • "The authors of [3] consider task scheduling while improving system performance by applying different voltage levels to the cores. The authors of [4] propose a task assignment scheme that takes cache behavior into consideration. "
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    ABSTRACT: As the industry moves from single- to multicore processors, the challenges of how to reliably design and analyze power delivery for such systems arise. We study various workload assignments to cores and their effect on the global power supply noise and ground bounce. We provide a detailed analysis of single and multiple cores and develop analytical formulas to capture the power supply noise and ground bounce of the system. We introduce metrics to estimate the amount of noise propagated from core to core and propose a supply noise aware workload assignment method. In our experiments, we show that timing constraints can be significantly affected if workload assignments are not properly made.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12/2011; 19(12):2243-2255. DOI:10.1109/TVLSI.2010.2080694 · 1.36 Impact Factor
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    • "The proposed method uses an offline characterization of the system power and performance for target application and a hill-climbing search method to find the optimal solution, and therefore is costly to be a general purpose runtime power management technique. Reference [15] formulates the problem of minimizing total power consumption of a multicore system subject to a throughput constraint by means of dynamic voltage scaling and task scheduling, and proves it to be NP-hard. A heuristic is then presented for the case of queued tasks, which is based on performing exhaustive search in the state transition space at each task execution point. "
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    ABSTRACT: In a multi-core system, power and performance may be dynamically traded off by utilizing power management (PM). This paper addresses the problem of minimizing the total power consumption of a Chip Multiprocessor (CMP) while maintaining a target average throughput. The proposed solution relies on a hierarchical framework, which employs core consolidation, coarse-grain dynamic voltage and frequency scaling (DVFS), and task assignment at the CMP level and fine-grain DVFS based on closed-loop feedback control at the individual core level. Our experimental results are very favorable showing noticeable average power saving compared to a baseline technique, and demonstrate the high efficacy of the proposed hierarchical PM framework.
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    • "In recent years, many researchers have proposed several DVS-based algorithms for applying to hard real-time systems [3] [4] [5] [6] [7] [8]. Lin et al. proposed an algorithm that is Genetic Algorithm for the DVS scheduling [4]. "
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    ABSTRACT: With the growing of applying the embedded system technology to the mobile systems, energy efficiency is becoming an important issue for designing a real-time embedded system. One of the possible techniques to reduce energy consumption is the Dynamic Voltage Scaling (DVS). In recent years, many researchers have proposed several DVS-based algorithms for applying to hard real-time systems. However, those methods are all based on the static scheduling. In this paper, a dynamic scheduling scheme with the Excenics-based Dynamic Voltage Scaling (E-DVS) mechanism has been proposed. In the proposed method, an extenics relational function is derived to calculate and predict the execution time and the system supply voltage. The experimental results show that the proposed method can effectively decrease the energy consumption about 78.81 percent.
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