Conference Paper

Redundancy and Test-Pattern Generation for Asynchronous Quasi-Delay-Insensitive Combinational Circuits

Univ. of Edinburgh, Edinburgh;
DOI: 10.1109/DDECS.2007.4295316 Conference: Design and Diagnostics of Electronic Circuits and Systems, 2007. DDECS '07. IEEE
Source: IEEE Xplore

ABSTRACT Most of the early work on testing asynchronous combinational circuits ignored faults inside C elements, a common building block in these circuits. Using a standard cell based design, where C elements are built using majority gates, we show that a number of faults are untestable in some implementations, while others are undetected by previously proposed tests, which yield a fault coverage of only 70-80% even in the small circuits examined here. We present a novel test pattern generation algorithm based on the D algorithm and time-frame expansion that can automatically detect all testable stuck-at faults in these families of combinational asynchronous circuits. Finally we present a comparison of the test pattern lengths achieved by this method with previously published full-scan based methods.

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