Redundancy and Test-Pattern Generation for Asynchronous Quasi-Delay-Insensitive Combinational Circuits
ABSTRACT Most of the early work on testing asynchronous combinational circuits ignored faults inside C elements, a common building block in these circuits. Using a standard cell based design, where C elements are built using majority gates, we show that a number of faults are untestable in some implementations, while others are undetected by previously proposed tests, which yield a fault coverage of only 70-80% even in the small circuits examined here. We present a novel test pattern generation algorithm based on the D algorithm and time-frame expansion that can automatically detect all testable stuck-at faults in these families of combinational asynchronous circuits. Finally we present a comparison of the test pattern lengths achieved by this method with previously published full-scan based methods.
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Article: Self-Timed is Self-Checking[show abstract] [hide abstract]
ABSTRACT: Self-checking circuits detect (at least some of) their own faults. We describe self-timed circuits, including combinational logic and sequential machines, which either halt or generate illegal output if they include any single stuck-at faults. The self-timed circuits employ dual rail data encoding to implement ternary logic of 0, 1, and unde fined states; the fourth state is used to signal illegal output and is shown to result only from certain circuit faults. The self-timed circuits also employ four-phase signaling according to a well-defined protocol of communications between the circuit and its environment; failures due to certain faults prevent the circuit from communicating properly, thus causing the circuit to halt. We show that any single stuck-at fault falls in either the first or the second category, thus providing complete fault coverage through self checking. No hardware needs to be added to our circuits to achieve the complete selfchecking property; further, the circuit is ...Journal of Electronic Testing 06/1997; · 0.45 Impact Factor
- 01/1990; Computer Science Press., ISBN: 978-0-7167-8179-0
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ABSTRACT: In this paper, we relate the property of semi-modularity to the testability of speed-independent circuits. We show that, under the pure chaos delay model, live speed-independent circuits that are strongly connected and composed of ANDs, ORs, and C-elements (with a possible inverter on each gate input) can be decomposed into a set of semi-modular circuits and therefore fully testable for certain classes of output stuck-at-faults (OSAFs). In addition, we show that a subclass of such speed-independent circuits are fully testable for all multiple OSAFs and for certain input SAFs (ISAFs) as well. Specifically, we qualify the kind of SAFs that are detectable during the normal operation of speed-independent circuits regardless of individual gate delays. These results demonstrate the inherent self-checking property of speed-independent circuits and indicate the kind of faults for which speed-independent circuits can be easily tested. We also present a CAD tool that checks the testability of a speed-independent circuit.Integration, the VLSI Journal. 01/1992;