Dynamic Current Testing for CMOS Domino Circuits

Abstract

In this paper, we propose a method for testing domino CMOS circuits using the transient power supply current. The method is based on monitoring the peak value of the transient current. We also present a test vector generation algorithm for testing large domino circuits. We evaluate the effectiveness of this testing method through simulations of various domino circuits of different sizes. Furthermore, we develop and implement a clustering technique to improve the fault coverage of the test method when used with large circuits. The algorithm divides the circuit into different clusters where each cluster is fed by a different power supply branch.

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DYNAMIC CURRENT TESTING FOR CMOS
DOMINO CIRCUITS
Anis Nazer
Department of Electrical and Computer Engineering
American University ofBeirut
Beirut 1107 2020, Lebanon
chehab@aub.edu.lb
Ali Chehab
Ayman Kayssi
Abstract- In this paper, we propose a method for testing
domino CMOS circuits using the transient power supply
current. The method is based on monitoring the peak value of
the transient current. We also present a test vector generation
algorithm for testing large domino circuits. We evaluate the
effectiveness of this testing method through simulations of
various domino circuits of different sizes. Furthermore, we
develop and implement a clustering technique to improve the
fault coverage of the test method when used with large circuits.
The algorithm divides the circuit into different clusters where
each cluster is fed by a different power supply branch.
I.
INTRODUCTION
The number of resistive-open defects in integrated circuits is
increasing with the latest technologies as the feature sizes are
reduced and the circuit complexity is increased. The reduction in
feature size has brought in new types of defects not effectively
modeled by traditional fault models [1, 2]. Hence, there is an
increased need for new test methodologies
detection of these defects. To improve defect coverage,
methods based on the quiescent power supply current (IDDQ) have
been widely used to complement traditional testing techniques [3-
6]. However, with very deep submicron technologies the total
background leakage current is increasing sharply and as a result, it
is degrading the quality of IDDQ tests. Techniques based on
monitoring transient supply currents provide a good alternative [7-
10]. Such test methods offer many advantages such as detecting
defects that escape other methods. Moreover, the traditional testing
techniques for static CMOS circuits are unfortunately not suitable
for the testing of dynamic CMOS circuits with resistive open
defects. IDDQ testing requires a constant flow of current through
conducting transistors to detect a fault, and hence, does not yield
efficient results in dynamic circuits where current conduction
depends on the clock logic, specifically in domino circuits [11, 12].
However, resistive-open defects can result in a noticeable change
in the transient current, iDDT. Furthermore, as current based tests
only require defect excitation, they allow for 100% observability,
and they result in easier test generation. Usually only few vectors
are enough to achieve reasonably-high fault coverage [13].
Previous results showed a high rate of defect detection using
iDDT in relatively small CMOS domino circuits [14]. In this paper
we apply iDDT testing to larger CMOS domino logic circuits. We
further assess the detection capability of iDDT by performing fault
to
facilitate the
test
simulations on medium-sized ISCAS'85 benchmark circuits, re-
implemented using dominologic. We propose
technique that divides the circuit in such a way to limit the
switching activity in each cluster, and that considerably increases
defect coverage.
This paper is organized as follows: in section 2, we review
previous work on current based testing and testing of domino
circuits. In section 3, we propose a test for CMOS domino circuits
using the transient current iDDT. In section 4, we evaluate the
effectiveness of the proposed test method by performing fault
simulation on various domino circuits of different sizes and
variable process parameters. We also discuss an automation system
to simulate many defects, collect and analyze the results. In section
5 we propose a circuit clustering algorithm to enhance defect
detection of iDDT in large circuits and we conclude in section 6.
a clustering
II.
PREVIOUS WORK
The iDDT testing is based on monitoring and analyzing the
transient current. The feasibility of iDDT testing has been proposed
in [15, 16] and it is shown to be capable of detecting certain
defects that cannot be detectedbyIDDQ and other methods [17].
The majority of test methods that are used to test
domino
circuits
target
delay
problems. A technique to derive test vectors that exercise the worst
case delay effects in a domino circuit in the presence of crosstalk is
described in [18]. Kundu et al. [19] present a timed test generation
methodology for CMOS domino circuits that assigns the circuit
inputs so that capacitively-coupled aggressors of a victim line
transition in time proximity which creates a noise effect that is
propagated within the clock cycle constraint. The authors in [20]
address testing of delay faults in domino circuits and identify
structures in both the "evaluate" and the "precharge" logic that
should be tested for delay faults. They propose conditions to
generate delay tests for them. In [21], the authors present a
technique for detection of delay faults in CMOS. It is based on a
testable design ofCMOS gates and on an algorithm developed for
detection of transistor stuck-at faults (stuck-open and stuck-on).
The methodology can be applied to both static and dynamic CMOS
gates. Chang et al. [22] propose a method for detecting bridging
faults in dynamic CMOS circuits. The method gives similar results
with respect to resistive shorts for domino circuits [23]. A new
approach for the detection of bridging faults in CMOS domino
logic circuits is presented in [24]. It is based upon the transient
faults and
charge sharing
1-4244-0173-9/06/$20.00 ©2006 IEEE.
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current that is sourced by the power supply rail of the inverter in
the domino logic gate during a low-to-high output transition. In
[25] and [26], the authors describe a method to measure the
sensitivity ofthe charge sharing problem for a domino gate. Also a
test vector generation algorithm and an algorithm to compact the
number oftest vectors are provided. Heragu et al. [27] developed a
model for analyzing charge sharing that avoids costly simulations.
The model is used to generate test vectors using a generalized
ATPG tool.
III.
PROPOSED TESTING METHOD
After setting the primary inputs of the circuit under test
(CUT), the clock signal is switched from 0 to 1 followed by a
transition from 1 to 0. This causes two current spikes, one per
transition. The peak value of every resulting current spike in the
CUT is compared to the peak current value in the fault-free circuit.
Ifthe peak value falls outside a pre-determined range, the circuit is
considered defective. The range in our case is expressed as a
percentage difference (p %), such that a current within + p % of
the expected magnitude is acceptable. The selection ofp depends
on process variations and anticipated noise and it directly impacts
the fault coverage. The value of p has to be chosen carefully
because a small p results in declaring good chips as defective
while a large p results in passing defective chips.
To determine a value for p that provides adequate
coverage, we performed circuit simulations and sensitivity analysis
over different process parameters and transistor sizes. The analysis
was performed for the following process parameters:
fault
*
*
*
Wn /Wp:NMOS / PMOS channel width.
"
Minimum channellength
VTHon/VTHOP
The parameters were varied over the range ±10%. For
example ifWpis increased by 10%, the peak value will change by
6.9% for the first spike and 5.7% for the second spike. After
examination of the results we note that the variation in the current
peak is always less than 10%. So a reasonable value for p that
would account for this variation would be IO%.
In this work we target resistive open circuit defects in CMOS.
Opens are probably the most difficult of all CMOS defects to
diagnose using any of the current device testing techniques.
Opens can be caused by missing conducting material or by
extra insulating material so that a single electrical node is
separated into multiple nodes [28]. An open circuit can occur
in any of the interconnect materials affecting either the gate,
drain or source connections. A simulation study conducted
by Rodriguez-Montanes et. al [29] using SPICE shows that
the stuck-at fault model is not suitable to model opens due to
capacitive coupling and leakage.
In this work we inject resistive open defects in various
locations in the circuit. The resistive opens are modeled as
resistor values ranging from 50k to 2000k.
threshold voltage ratio
A.
Capacitive Coupling in Domino Circuits
In a domino circuit, a coupling capacitance exists between the
gate terminals of the P-channel MOSFETs and the VDD supply.
These gate terminals are all connected to the same clock line.
When the clock signal switches, current flows in this capacitance
and affects the transient power supply current. In small circuits
( 10 gates), the effect of this capacitive coupling is negligible.
However, this is not the case when the circuit size increases to
hundreds of gates. As a matter of fact, the coupling current
becomes dominant, and masks the transient current that is due to
gate switching. For example, when we switch the C432 circuit, we
get a switching current of approximately 800 uA on top of a 1.25
mA coupling current. This significantly degrades the ability of the
proposed iDDT method to detect faults. However, when we subtract
the coupling current, we obtain a waveform that highlights the
current component due to gate switching and hence can be used for
defect detection.
B.
Conversion to Domino
The non-inverting nature of domino logic gates requires the
synthesis of a logic circuit without the use of inverters, except at
the primary inputs, or at the outputs. This is a fundamental
constraint that forces the circuit synthesis algorithms to push the
inverters towards the primary inputs of the circuit. It may happen
that some inverters cannot be "pushed back," in which case circuit
duplication is performed to get both positive and negative logic.
Therefore, the size of the resulting circuit increases, compared to
the original circuit, but is guaranteed to be less than twice the
original size. Note that the number of logic levels in the network
does not change [30]. Although an algorithm exists for minimizing
the duplication penalty in terms of area [31], we chose to
implement a straightforward approach and then use the Berkeley
SIS software to optimize the circuit area.
C.
Test Vector Generation
For the purpose of efficient testing and adequate
coverage, the input test vector should exercise a single VDD-to-
GND path in a certain domino gate in the CUT, thus covering
faults inserted along this path between VDD and GND. This input
vector should also minimize the switching activity in the rest ofthe
circuit. To find the input vector that will excite a certain fault, we
use linejustification based on controllability values [32].
To improve the detection of iDDTbased testing, the don't-care
inputs are chosen in such a way to minimize the switching activity
in the circuit. For domino logic, all the don't cares should therefore
be set to logic "0". Due to the duplication during the circuit
synthesis phase,
independently,
since some primary inputs are in reality just
inverted versions of other primary inputs. However, it may still be
possible to set all don't care inputs to logic "0" independently, if
for example, the inputs come from the flip-flops of a scan chain.
Effect ofProcess Variation
A significant limitation of any iDDT test is that process
variations can cause the transient current to vary substantially, thus
leading to a range of responses for the same fault-free circuit. In
actual circuits, the parameters of a transistor vary from wafer to
wafer, or even between transistors on the same die. Consequently
the quality of the transient current methods is markedly degraded
by process variations which cause the current consumed by a fault
free circuit to vary considerably. A scaling procedure is applied to
overcome the effects of process variation [33]. The procedure was
previously applied to static CMOS circuits and results show that
the impact of process variation was suppressed by using this
scaling procedure.
Other Detection Criteria
To study how well the iDDT test method performs, we compare
it with two other criteria. The first is based on the accumulated
fault
it may not be possible
toset the inputs
D.
E.
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charge during switching, and the other is based on the gate delay.
The following is a brief description ofeach method:
*
Accumulated charge: In this test, the integral of the
transient current waveform in the CUT is calculated
and compared to that of the defect-free circuit. The
integral is calculated after removing the capacitive
coupling and evaluated over each current spike; if
the charge difference between the CUT and the-fault
free circuit is not within III% for either spike, the
circuit is considered defective.
*
Gate delay: In this case, the delay of the gate, taken
from the falling edge ofthe clock to the output ofthe
gate, is measured and compared to the delay of the
gate in the good circuit. If the delay value falls
outside + III % ofthe good circuit value, the circuit is
considered defective. In addition to the gate delay,
we check the voltage failure, i.e. the case where the
gate output is supposed to drop but does not drop
due to the defect. In the case of large circuits, the
failure is measured at the output of the gate, not at
the primary output of the circuit. We note here that
those criteria are not test methods, but serve as
measures to compare with iDDT.
IV.
SIMULATION RESULTS
All simulations were performed using HSPICE with different
TSMC 0.18 micron process parameters, obtained from the MOSIS
website
resistors (50k, 100k, 500k, 1000k, and 2000k) in various locations
in each circuit.
Simulations ofa Carry Adder Circuit
The CUT in this case is a four-stage ripple carry-adder circuit.
We inject resistors at various positions at each stage. We test the
circuit with test vectors that excite the defects. Testing is also done
for four different processes.
For lack of space, we show in Table
simulations for faults inserted in the first stage only. We indicate
the percentage of the defects detected by spike 1, spike 2, either
spike, defects that cause a failure, and defects that cause 10%
delay.
The results show that the iDDT testing method detects a high
percentage of the injected defects. Another useful result that is not
shown in the table is that any input combination that exercises a
path in the NMOS block of the CUT would detect, using spike 2,
all faults in the PMOS block, except those pertaining to the keeper.
Moreover, iDDI-based testing provides better coverage than delay
test and voltage test for stage 1 and for all the other stages of the
circuit.
[34]. We modeled resistive open faults by injecting
A.
1 the results of the
TABLE I.
PERCENT COVERAGE FOR FAULTS IN STAGE ONE
Process
tlch
tlax
tl4b
t24i
I~
---
IL
2-1
Spikel
71.25
72.5
71.25
71.25
Spike2
78.75
81.25
78.75
78.75
Both
87.5
90
87.5
87.5
'Ii
I
Fail
56.25
56.25
56.25
56.25
I
I
Delay
48.75
48.75
48.75
48.75
B. Simulation Automation
When simulating a large number of defects
thousands) becomes
simulations and gather and analyze the results manually. So we
implemented a system to automate the process of generating the
SPICE files, injecting the defects in the circuit, running the
simulation, storing the simulation output, processing the output
signals, and finally gathering and analyzing the results.
We used three software programs to build the system:
*
C++ codes to execute the algorithms involved in the
testing process,
"bdnet" format to SPICE, generating the test vectors,
clustering the circuit, and generating the ".alter"
statements for the various simulations.
(order of
performitpractically impossible
to
i.e.
converting the circuit from
*
HSPICE to run the actual simulations.
MATLAB to invoke HSPICE to run the simulations,
invoke the executables, store the simulations in a
special directory structure, read the output files of
HSPICE
andperform
integration, subtraction, ... etc) and take the pass/fail
decision ofthe test methods.
*
some
processing(ex.
C.
Simulations ofthe C432 Circuit
We used the automation system mentioned above to simulate
a large number of defects in the C432 circuit implemented in
domino logic.
In addition to iDDT, delay, and failure tests, we also monitor
the accumulated charge under the modified iDDT signal waveform,
after removing the capacitive coupling current component. We
assume in this case that all inputs can be set independently, to
minimize the switching activity in the circuit.
We injected defects in 206 gates. On average, for each gate
we injected defects in 26 different fault locations. The obtained
results show that a high detection rate can still be achieved even
for large circuits. However the detection of iDDT based test
degrades as the switching activity increases. For a switching
activity of 20, only 20% ofthe faults are detected by iDDT.
V.
CIRCUIT CLUSTERING
To enhance the detection for large circuits we suggest a
clustering algorithm that partitions the circuit in such a way to
limit the switching activity in each cluster and hence to ensure
better fault coverage. The power supply will have different
branches, one per cluster. Hence, the gates in the same cluster will
share the same power supply branch. The gates will be clustered in
a way such that the maximum number of switching gates in one
cluster does not exceed a specific parameterized value.
We start by applying the set of test vectors to the CUT. For
each vector we count the number of gates that switch, (we refer to
this number as the switching activity). Then we select the vector
having the maximum switching activity (Amax) and we check ifthe
maximum switching activity is higher than the desired value (Ath).
In this case, we split the gates that have switched by this vector
into two clusters. The remaining gates that did not switch will be
distributed randomly into those two clusters. Next we recalculate
the switching activity for each vector, only this time the switching
activity for a test vector will be the number of gates that switch
inside the cluster where the gate under test resides. We then select
the vector having the maximum switching activity and we compare
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with the desired activity. If the activity is still larger than the
desired value, we repeat the process until we reach the required
switching activity.
The algorithm was applied to the C432
converted to domino logic as described earlier. The resulting
circuit contains 339 gates and has a maximum switching activity of
152. We applied the algorithm for different and increasing values
of allowed switching activities and this led to decreasing numbers
of clusters, where at the extreme point we have 106 clusters with a
maximum switching activity of one.
circuit.
It was
A.
IDDTwithClustering
To show the improvement in the testing method after
clustering, we apply the algorithm to the C432 circuit with a
maximum activity set to 10 gates. Next we perform simulations on
the circuit before and after clustering. The simulations were
performed for 64 gates constituting two clusters. Defects were
injected at 26 different locations in each gate covering almost all
the nodes in the gate.
The simulation results are shown in Table 2. The results are
averaged over all the injected defects of the 64 simulated gates.
The first column in the table shows the resistive values, the
following columns indicate the detection using iDDT, gate delay,
gate failure, and accumulated charge respectively. The percentages
shown are averaged for all the 64 gates. We note that clustering
the circuit improves iDDT detection from 37% to 69% and charge
detection from 44% to 77%. This result confirms that clustering
the circuit will significantly improve the detection capability of the
iDDT based testing methods, making the clustering technique
worthwhile.
B.
Clustering Overhead
It should be noted that iDDT based testing could be
performed through the use of external or built in current sensors.
When using built-in current sensors, there will be an area overhead
impact on the chip due to the area occupied by the current sensors
and the required routing. When we apply the clustering technique,
every additional cluster will require, in principle, a separate sensor
leading to higher area overhead. In general, the area overhead
depends on the following factors:
*
The area occupied by the sensor itself
*
The area used for the routing ofthe VDD and GND pins.
*
The number of clusters
Although clustering the circuit requires an area overhead, the
clustering technique greatly enhances defect detection. The cost of
the additional chip area is therefore justified by the improved chip
testability.
VI.
CONCLUSION
We proposed a new test method to detect resistive open
defects in domino circuits. The proposed method is based on
monitoring and analyzing the dynamic power supply current, iDDT.
The method is also immune to process variation after applying a
scaling procedure. We presented an algorithm to generate test
vectors suitable for current based testing; it is based on minimizing
the switching activity in the circuit. We also suggested a technique
to remove the capacitive coupling from the transient current
waveform to enhance the detection capability of the test method
especially in large circuits where the effect of capacitive coupling
masks the transient current.
We evaluated the effectiveness of iDDT testing for small
domino circuits and on the C432 circuit. We injected defects,
modeled as resistors of different values, at various locations in the
circuit. The results showed high detection rates, especially for
large resistor values, and for low switching activity. For high
switching activity, iDDT defect detection degrades significantly.
We implemented a system that automates the process of
generating the SPICE files, injecting the defects in the circuit,
running
the
simulations,storing
processing the output signals, and finally gathering and analyzing
the results.
Furthermore, we developed and implemented in software a
clustering technique to improve the fault coverage of the test
method when used with large circuits.
Finally, we verified the clustering technique on ISCAS'85
benchmark circuits. The results showed that when using clustering,
the fault coverage improves considerably.
thesimulations
outputs,
TABLE II.
IDDT DETECTION BEFORE CLUSTERING AND AFTER CLUSTERING
Before clustering
delay
60.3%
61.4%
61.7%
61.1%
After clustering
delay
60.4%
61.5%
61.8%
61.2%
spike 1
26.1%
26.7%
27.0%
26.6%
spike 2
25.9%
26.6%
27.7%
26.7%
1DDT
36.1%
36.8%
37.6%
36.8%
fail
35.9%
40.2%
45.7%
40.6%
charge 1
30.1%
35.5%
41.30%
35.6%
charge 2
24.2%
30.3%
35.6%
30.0%
charge
38.4%
44.5%
50.6%
44.5%
500k
1000k
2000k
Average
spike 1
47.4%
47.9%
48.4%
47.9%
spike 2
54.5%
54.7%
55.0%
54.7%
iDDT
69.0%
69.5%
69.7%
69.4%
fail
35.9%
40.3%
45.8%
40.7%
charge 1
55.5% 0
64.3%
67.3%
62.3%
charge 2
48.8%
54.0%
62.0%
54.9%
|
charge
70.8%
78.0%
81.4%
76.7%
500k
1000k
2000k
Average
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