Ultra-Low-Power SRAM Design In High
Variability Advanced CMOS
AUG 07 2009
Submitted to the Department of Electrical Engineering and Computer
in partial fulfillment of the requirements for the degree of
Doctor of Philosophy
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
@ Massachusetts Institute of Technology 2009. All rights reserved.
Department of Electric
ngineering and Computer Science
May 5, 2009
C ertified by ...............
Anantha P. Chandrakasan
Joseph F. and Nancy P. Keithley Professor of Electrical Engineering
Accepted by ..........................
Terry P. Orlando
Chairman, Department Committee on Graduate Theses
Ultra-Low-Power SRAM Design In High Variability
Submitted to the Department of Electrical Engineering and Computer Science
on May 5, 2009, in partial fulfillment of the
requirements for the degree of
Doctor of Philosophy
Embedded SRAMs are a critical component in modern digital systems, and their role
is preferentially increasing. As a result, SRAMs strongly impact the overall power,
performance, and area, and, in order to manage these severely constrained trade-offs,
they must be specially designed for target applications. Highly energy-constrained
systems (e.g. implantable biomedical devices, multimedia handsets, etc.) are an
important class of applications driving ultra-low-power SRAMs.
This thesis analyzes the energy of an SRAM sub-array. Since supply- and threshold-
voltage have a strong effect, targets for these are established in order to optimize
energy. Despite the heavy emphasis on leakage-energy, analysis of a high-density
256x256 sub-array in 45nm LP CMOS points to two necessary optimizations: (1) ag-
gressive supply-voltage reduction (in addition to Vt elevation), and (2) performance
enhancement. Important SRAM metrics, including read/write/hold-margin and read-
current, are also investigated to identify trade-offs of these optimizations.
Based on the need to lower supply-voltage, a 0.35V 256kb SRAM is demonstrated
in 65nm LP CMOS. It uses an 8T bit-cell with peripheral circuit-assists to improve
write-margin and bit-line leakage. Additionally, redundancy, to manage the increas-
ing impact of variability in the periphery, is proposed to improve the area-offset
trade-off of sense-amplifiers, demonstrating promise for highly advanced technology
nodes. Based on the need to improve performance, which is limited by density con-
straints, a 64kb SRAM, using an offset-compensating sense-amplifier, is demonstrated
in 45nm LP CMOS with high-density 0.25 pm2 bit-cells. The sense-amplifier is re-
generative, but non-strobed, overcoming timing uncertainties limiting performance,
and it is single-ended, for compatibility with 8T cells. Compared to a conventional
strobed sense-amplifier, it achieves 34% improvement in worst-case access-time and
4x improvement in the standard deviation of the access-time.
Thesis Supervisor: Anantha P. Chandrakasan
Title: Joseph F. and Nancy P. Keithley Professor of Electrical Engineering
MIT is truly a unique and wonderful place on this earth. For a new graduate student,
as I once was, it can easily be too wonderful and too big. The only way to realize your
place at MIT is through the guidance, encouragement, support, and friendship of an
outstanding advisor like Prof. Anantha Chandrakasan. First and foremost, I thank
Anantha. When I arrived here, I was not sure what, if anything, I could accomplish.
Anantha, convinced me, by always expecting more from me, by always challenging me,
and by supporting me through every research endeavor, that I could be a contributing
member of this great community. His lessons for me have gone far beyond circuits;
he has taught me to be a critical, sincere, cooperative, and respectful researcher.
Anantha works firstly for his students, and I have learned more by watching him than
I ever will from reading volumes of journals. As I proceed in my career, Anantha will
always play an important role; he has given me something to strive for technically
and personally. Thank you, Anantha, for your always strong support and guidance.
I am eternally grateful to my thesis committee members, Prof. Charlie Sodini
and Prof. Duane Boning. Every researcher offers his work to the community hoping
it is received by someone. To be able to discuss my work with such outstanding
researchers as Charlie and Duane is the greatest honor of my career. Charlie and
Duane have given this thesis a level of attention that has made the effort more than
worthwhile. Thank you for your feedback and support, which has always aimed to
make this thesis better. Because of your input, I am much prouder of this work, and
after the many years it has consumed, that means a lot!
There are several faculty at MIT who have had a profound impact on me both
technically and non-technically. I am extremely grateful to Prof. Harry Lee, who's
mastery of circuits, and the ability to make that mastery accessible, has inspired me
to study every last aspect of my field. I am grateful to Prof. Al Oppenheim who,
by example, has shown me the impact that excellence in teaching can have and the
level of dedication that must applied. I thank Prof. John Guttag for encouraging me
to enthusiastically and intrepidly venture into new fields to seek out for myself how I