Negative bias temperature instability (NBTI) has emerged as a major reliability degradation factor in nano-scale CMOS technology. In this paper, we analyze the impact of NBTI degradation in both the maximum operating frequency (fMAX) and the total standby leakage current (IDDQ) of digital CMOS circuits. Our analysis shows that due to NBTI, both fMAX and IDDQ reduce with time with a fix exponent of 1/6 (~t1/6). Based on this analysis, we develop temporal fMAX-IDDQ model and apply it to several ISCAS'85 benchmark circuits designed using BPTM 70nm file. Results show that fMAX and IDDQ can reduce by more than 8% and 30% in 3 years operation time, respectively. Furthermore, we show that fMAX and IDDQ degradations are highly correlated throughout the operating lifetime, and using this fact, one can avoid expensive fMAX testing and predict fMAX degradations as a function of IDDQ measures.
"Although all the above proposed schemes measure NBTI impact, they require significant area overhead and/or possess lower accuracy. For example, transistor parameters monitoring    for a larger group of PMOS transistors that degrade at different rates require enormous area overhead . Similarly, the circuit parameters monitoring schemes   lack accuracy in measuring NBTI impact because the monitoring results include the effects of all the degradation mechanisms. "
[Show abstract][Hide abstract] ABSTRACT: Negative Bias Temperature Instability (NBTI) has become one of the major threats to circuit reliability in nanoscale-era. This paper presents a novel technique to monitor and tolerate NBTI in nanoscale circuits. First, it models NBTI impact on the gate output transition time, the simulation results show that NBTI can cause up to 8.56% increment to the transition time. Second, it presents a scheme to monitor the NBTI impact, the scheme is based on measuring transition time of the gate output. The proposed scheme converts the transition time increment into a voltage with a sensitivity of 0.50mV = ps, the simulation results show that the transition time increment can cause up to 80mV increment in the monitoring circuit output voltage. Third, it proposes a design for reliability technique to mitigate NBTI impact by applying a positive body bias to the PMOS transistors, simulations carried out on a 33-stage ring oscillator reveal that the technique reduces NBTI impact by 34% in 10 years operational life. To show its effectiveness, leakage overhead of the proposed technique is also analyzed.
2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011; 01/2011
[Show abstract][Hide abstract] ABSTRACT: NBTI is a serious reliability concern in state of the art PMOSFET devices. The implementation of nitrided gate oxides to prevent boron penetration has aggravated the NBTI issue. Because of relaxation effects careful stress and measurement techniques (ldquoOn-the-Flyrdquo) must be used for reliable estimation of device lifetime. This abstract describes a unique enhanced NBTI degradation phenomenon in which NBTI induced V<sub>T</sub> degradation was determine to be directly proportional to the initial V<sub>T</sub> of the device. Electrical results from special test structures identified halo implant channeling as causing the enhanced NBTI induced degradation behavior.
[Show abstract][Hide abstract] ABSTRACT: NBTI and CHC are two leading reliability concerns. Their degradation rate, which is represented by the time exponent (n), varies with multiple factors, such as the measurement method and bias voltages (i.e., different n for sub-threshold or linear current). Such a variation significantly affects the long-term prediction of circuit lifetime. By investigating the underlying mechanisms and silicon data, we conclude that the bias dependence is due to intrinsic device non-linearity. With a unified aging model of threshold voltage (Vth) shift, different time exponents in different operation regions are consistently explained. The proposed solution captures the change of n under various supply voltages (Vdd), as validated with silicon data from transistors and RO measurement. It helps improve the accuracy in reliability prediction, reducing unnecessary design margins. Based on the result, the device and circuit lifetime is expected to be enhanced operating at lower Vdd due to the reduction in the time exponent.
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