An optimized direct digital frequency synthesizer based on even fourth order polynomial interpolation

Abstract

In this paper, an optimized direct digital frequency synthesizer (DDFS) utilizing even fourth order polynomial is introduced. The spurious free dynamic range (SFDR) upper bound of the design is evaluated and an optimized digital system is designed to implement the method. It is shown that SFDR of the implemented digital system is 72.2dBc, which is only 2.15dBc less than the theoretical SFDR upper bound. Finally, the proposed system is realized in a chip using a 0.13mum standard cell library. The maximum clock frequency, the chip area and the chip power consumption are calculated equal to 210 MHz, 1048mum² and 11.57 muW/MHz, respectively

Full text

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An Optimized Direct Digital Frequency Synthesizer Based on
Even Fourth Order Polynomial Interpolation
Ashkan Ashrafi
Department of Electrical and Computer Engineering
The University of Alabama in Huntsville
ashkan@ieee.org
Reza Adhami
Department of Electrical and Computer Engineering
The University of Alabama in Huntsville
rradhami@eng.uah.edu
Key Words: Direct Digital Frequency Synthesizer, Polynomial Interpolation, Spurious Harmonic Analysis
Abstract?
frequency synthesizer (DDFS) utilizing even fourth order
polynomial is introduced. The spurious free dynamic
range (SFDR) upper bound of the design is evaluated
and an optimized digital system is designed to implement
the method. It is shown that SFDR of the implemented
digital system is 72.2dBc, which is only 2.15dBc less than
the theoretical SFDR upper bound. Finally, the proposed
system is realized in a chip using a 0.13? ?m standard cell
library. The maximum clock frequency, the chip area
and the chip power consumption are calculated equal to
210MHz, 10481? ?m2 and 11.57 ? ?W/MHz, respectively.
? In this paper, an optimized direct digital
I. INTRODUCTION
In modern
frequency synthesizers (DDFS) play an important role. They
are employed to create an accurate sinusoidal signal and
because of their sub-hertz frequency resolution and fast
frequency hopping, they are ideal choices for spread
spectrum and radar systems. In a DDFS, the amplitude of a
sinusoidal signal is digitally stored in a ROM and they are
consecutively fetched by the output of an accumulator,
which feeds the address line of the ROM [1]. Fig.1 shows
the structure of a DDFS.
communication systems, direct digital
Fig.1: Block diagram of a DDFS system.
The input of the accumulator and its wordlength
determine the output frequency and its resolution,
respectively. The frequency of the output sinusoidal signal is
F
f
2
where,, and are the input of the accumulator, the
accumulator wordlength and
respectively [1].
Unfortunately, ROM-based DDFS systems have two
major drawbacks, high power consumption and low
maximum clock frequency. Both of these drawbacks are due
to the requirement of a very large ROM. These drawbacks
are further deteriorated by increasing the ROM size, which
enhances the frequency resolution and spurious free dynamic
range (SFDR) of the output sinusoidal signal. The SFDR is
defined as the ratio of the fundamental harmonic amplitude
to the maximum spur amplitude.
A basic method to reduce the ROM size of a DDFS is to
truncate the accumulator’s wordlength from
. This truncation causes a significant reduction in the
SFDR of the output signal. The SFDR of the resultant
structure is calculated in [2] for a non-quantized output and
is given by
dBc6 SFDR
W
?
.
Moreover, the output quantization signal-to-noise ratio
(QSNR) is given by [1]
dBc716 QSNR.D ??
.
Truncating the accumulator’s output cannot significantly
reduce the ROM size and further reduction is necessary if
design of a low power DDFS is to be attempted. The most
obvious method to reduce the ROM size is to use the quarter
wave symmetry of a sinusoidal signal. In this method, only
the information of the first quadrant of a sinusoidal signal
needs to be stored in a ROM. The other quadrants can be
produced by using the information of the first quadrant [3].
Several methods have also been introduced to generate the
first quadrant such as CORDIC method [3] and polynomial
interpolation methods [4].
clk
L
r
out
f
?
, (1)
the clock frequency,
r F
L
clk
f
to W where
L
LW ?
(2)
(3)
Proceedings of the
38th Southeastern Symposium on System Theory
Tennessee Technological University
Cookeville, TN, USA, March 5-7, 2006
MA5.2
0-7803-9457-7/06/$20.00 ©2006 IEEE.
109

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A method based on interpolating the first quadrant of the
cosine signal using quadruple angle formula, which is
actually an even fourth order polynomial, is introduced in
[5]. Although the proposed method has some advantages in
digital realization, its SFDR is evaluated incorrectly equal to
84dBc. The correct SFDR upper band of the above method
is evaluated in [6] where it is shown to be 41dBc. In [7], a
Chebyshev polynomial interpolation method is used to
design a DDFS based on an even fourth order polynomial
interpolation. The maximum SFDR of this method is
evaluated equal to 66.2dBc while the SFDR of the realized
system is 64dBc.
After several attempts to design a DDFS based on the
even fourth order polynomial interpolation, it seems
necessary to find the theoretical upper bound of the SFDR of
such a design. The SFDR upper
aforementioned DDFS structure is evaluated equal to
74.35dBc by a novel mathematical approach based on the
Chebyshev minimax problem in [8]. In this paper, a novel
digital system is introduced to realize the optimized DDFS
based on the even fourth order polynomial interpolation.
boundof the
II. ARCHITECTURE OF THE DDFS
The goal is to approximate the first quadrant of the
cosine signal
?
??
2
by an even fourth order polynomial
4
210
)(xcxccxP
???
,
0
? x
In [8], the coefficients of (5), which maximize the SFDR
of the final DDFS, are calculated as
5996070.99941104
1
?
c
The first step to determine the architecture of a DDFS is
finding a suitable value for the phase and the output
wordlengths. The maximum possible SFDR is 74.35dBc [8]
thus, according to (2),
wordlength of is suitable. On the other hand, the
output wordlength could be chosen according to the given
requirements, but the output quantization noise dominates
the spurious frequencies caused by the structure. Therefore,
according to (3) the output wordlength is chosen to be 12
(
12
?
D
). The accumulator wordlength is chosen equal to
.
25
?
L
To quantize the phase of the DDFS, first we should
rearrange (5) such that
)()(
210
xccxcxP
???
.
The variable x is the phase of the DDFS and varies in
the interval [0,1]. In reality, x should be shown in terms of
??
?
?
xxf cos)(
?
,. (4)
10
?? x
2
. (5)
1
?
5613540.22882340
3358226-1.2256545
3
2
?
?
c
c
. (6)
. Therefore, a phase
35.746
?
W
13
?
W
22
(7)
the actual phase of the DDFS or the truncated output of the
accumulator. Let’s define the phase of the DDFS by the
variable n, which varies in the interval
. Now the variable
] 12 , 0 [
actually quantized) in terms of the discrete variable n by
nn
x
W
?
or
] 1 2 , 0 [
2?
?
W
11?
x in (7) can be represented (or
112
22
??
,.(8)
120
11??? n
Obviously, the discrete definition of x is not exactly the
same as its continuous version. This is because of the
quantization process. By substituting (8) into (7), the phase-
quantized version of the polynomial can be obtained.
?
?
???
22
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
??
2
11
21
2
11
0
)(
n
cc
n
cnP
,. (9)
120
11??? n
Note that the amplitude of the polynomial is still one.
The next step is quantizing the coefficients of the
polynomial (6). Since the polynomial generates the first
quadrant of the sinusoid and it covers half of the amplitude
of the entire signal, it should be quantized by
bits. By multiplying (9) by
amplitude because the largest 11-bit number is
However, for the sake of simplicity, we will use
become obvious that choosing
difference because the final coefficients will be determined
by an optimization algorithm and their number of bits would
merely be a constraint on the algorithm. After the
multiplication, (9) would become
?
?
?
?
?
2
111??
D
, we can quantize the
1211?
1
. It will
211? .
11
2
would not make a big
11
2
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
??
2
11
11
2
11
1
2
11
0
11
2
222)(
n
cc
n
cnP
,. (10)
120
11??? n
Now the quantized coefficient can be evaluated by rounding
off the coefficients of the discrete polynomial (10).
Using the quantized coefficients, the discrete polynomial
(10) can be rearranged to the form
?
?
?
??
pnP
,
m ?
11
11
21
0
2
2
)(
?
?
?
?
m
ppm
11
2
2
n
,, (11a)
120
11??? n
where
p
??
5 . 0
?
211
?
The new variable m, is the result of a fixed-width 11-bit
squarer in which the wordlength of the input and the output
of the squarer are identical. The simplest method to realize a
kbit fixed-width squarer is to use a regular squarer and
truncate the least k significant bits of its output. This method
is definitely the most inefficient realization of a fixed-width
squarer.
The discrete polynomial (11a) is far from ready for
hardware realization. The term
is always less than one and it cannot be realized in a digital
system where the lowest nonzero number is one. To
overcome this problem, the entire parenthesis must be
quantized again. It has been found that a 6-bit quantization
ii
c
,
3 , 2 , 1
?
i
. (11b)
11
2m
inside the parenthesis
110

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would be adequate to obtain the closest SFDR to the upper
bound of 74.35dBc. Therefore, the discrete polynomial (11a)
can be rewritten as
?
?
?
To further simplify the polynomial (12), we can use the
integer powers of two as logical left or right shifts and
summation. To show the digital process we should use the
floor function.
?? .
?
?
?
?
2
In the discrete polynomial (4.15), the terms
have been found to be the best choices to achieve the most
optimized SFDR. According to (6), the coefficient
consequently the coefficient
polynomial (13) can be rearranged again to
?
??
?
?
2
Using (6) and (11b), the value of?
equal to 59. We will keep this number constant in the
process of optimization. The multiplication of 59 by?
can also be considered as logical right or left shifts and
summation as follows
?
?
??
22
According to (6) and (11b), the number
18-bit number, thus we can define
116
11
21
6
0
22
2
2)(
?
?
?
?
?
?
?
??
???
m
ppmpnP
. (12)
?
?
2
?
?
?
?
?
?
?
?
?
??
?
?
??
?
??
?
??
?
??
?
??
?
???
116
23
2
1
6
0
22
2
2)(
mp
pmpnP
. (13)
and
1c and
is negative, thus the discrete
32
2
1 p
?
?
?
?
?
?
?
??
?
?
?
??
?
?
??
?
??
?
??
?
??
?
??
?
???
116
23
2
1
6
0
22
2
2)(
mp
pmpnP
. (14)
?
3
22p
is calculated
?
2
2m
?
??
?
??
?
?
??
2 p is an
?
??
?
?
??
?
??
??
??
?
???
??
?
??
?
22
2
2
6
2
026
2
22
2
2
2222 59
mmmmm
. (15)
1
6
1
6
2 p as
qp
???
122
17
1
6
, (16)
where is a new integer variable. By substituting (15)
and (16) into (14) we can obtain
?
?
?
?
?
?
2
q
?
?
?
?
?
?
?
?
?
?
?
?
?
??
?
?
??
?
??
?
??
?
?
??
?
??
?
??
??
?
??
?
??
?
??
?
????
116
22
2
2
617
0
22
22
2212)(
mm
q
m
mpnP
. (17)
It is interesting that the term
17-bit logical not of the number
?
?
?
?
By utilizing the above method, we have been able to
eliminate the need of subtraction in the polynomial. The
only remaining subtraction will also be eliminated in the
final stage. In (18), there is a final multiplication by the 11-
bit variable m. The other multiplicand has 12 bits, therefore;
a bit multiplier is required. Since the output of the
multiplier is divided by, it would have only 12 bits. This
means a fixed-width multiplier is required.
A fixed-width multiplier has an output whose wordlength
is equal to its greatest input word-length (in this case the
, is in fact the
s
??1217
s thus
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
??
?
??
?
?
??
?
??
?
??
??
?
?
??
?
?
??
?
??
?
??
116
22
2
17
2
6
0
22
22
2
2
2not)(
mm
q
m
mpnP
. (18)
1112?
11
2
greatest is 12). The result of the multiplication is
theoretically a 12-bit number but calculations show that its
most significant bit is always zero. In this case, we can
ignore the most significant bit and consider the output of the
fixed-width multiplier as an 11-bit number. The fixed-width
multiplier given in [10] is used in the proposed design.
The discrete polynomial (18) just creates the first
quadrant of the sinusoidal signal. To complete the
architecture, a mechanism is required to produce the other
quadrants from the first quadrant. Moreover, an offset of
must be added to the final signal in order to have an
unsigned output. Unsigned output is necessary because
DAC’s normally accept an unsigned input. The following
Boolean function can produce the other quadrants in their
correct locations with respect to the first quadrant and add
the required offset to the signal
?? ?
120
) 1.(
pyZy out
?????
where
21
lly
??
, and
2ndmost significant bits and Z is the output of the fixed-
width multiplier with its most significant bit ignored.
The next step is to find the optimized values for the
coefficients and (the coefficient
to maximize the SFDR. To do the optimization, the entire
digital system is simulated as a function in MATLAB and
then the Nonlinear Nealder-Mead Simplex optimization
method [42] is used to find the best values for the
coefficients. The optimization algorithm found the following
coefficients
2041
0
??
p
Therefore, according to (16) the number
11
2
?
12
)
0
2048.(
py
?
, (21)
are respectively the 1
1l
2l
st and
is kept constant)
0
p
1 p
2
p
.2508
1
?
p
(22)
would be 29441.
q
Fig.2: The Spectrum of the proposed DDFS
(realized and ideal)
111

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Fig.3. The architecture of the DDFS
112

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The SFDR of the final design obtained by the
optimization algorithm is 72.2dBc, which is 2.15dBc lower
than the maximum theoretical value of 74.35dBc. Fig.2
shows the spectrum of the final DDFS output and the
spectrum of the signal obtained by the ideal case from (5)
using the coefficients (6).
The architecture of the entire DDFS is illustrated in
Fig.3. To reduce the critical path delay, the summer that
adds the numbers in (18) is realized by a carry-save adder
and a level of pipeline is incorporated in the design.
III. VLSI IMPLEMENTATION RESULTS
The proposed DDFS is designed up to the layout level
for one poly and 8 metal layers using TSMC 0.13?m 1.2V
standard cell library. The electrical characteristics of the chip
are compared with some of the recent designs [11] and [12].
Table-I shows the results of the comparison where we can
find the superior performance of the proposed DDFS over
the other state-of-the-art methods.
Table-I: Comparison between the proposed method and
some recent designs
DesignSFDR
(dBc)
Max Freq.
MHz
Power
?W/MHz
Area
?m2
Process
?m
This paper 72.2 21011.57 10481 0.13
[5], [6] 84.6 100135.3 310000 0.35
[11] 8415060090000 0.18
IV. CONCLUSION
A new DDFS architecture based on the even fourth order
polynomial interpolation is proposed in this paper. It is
shown that the structure of the DDFS provides the optimized
SFDR very close to the maximum theoretical value. The
proposed DDFS is also implemented in a chip using 0.13?m
technology. The electrical characteristics of the design are
superior compared to the recent reported state-of-the-art
DDFS systems.
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[5]
[6]
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[9]
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