A low-leakage high-speed monotonic static CMOS 64b adder in a dual gate oxide 65-nm CMOS technology
ABSTRACT In this paper, we investigate the use of monotonic static CMOS logic within a high performance carry look-ahead adder (CLA) in the context of a 65nm technology with significant leakage. The goal is a good compromise between speed, power, and noise immunity. We compare the monotonic static CMOS 64b CLA with domino and static CMOS adders with respect to speed and power consumption, using a predictive dual gate oxide 65nm technology with significant gate leakage. The comparison shows that monotonic-static CMOS is a potentially useful alternative in such applications. Compared to domino and static CMOS, it can provide advantages in evaluation speed and static power for a set of nominal gates sizes.
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Conference Paper: Forbidden transition free crosstalk avoidance CODEC design.[Show abstract] [Hide abstract]
ABSTRACT: In this work, we present a CODEC design for the forbidden transition free crosstalk avoidance code. Our mapping and coding scheme is based on the Fibonacci numeral system and the mathematical analysis shows that all numbers can be represented by FTF vectors in the Fibonacci numeral system (FNS). The proposed CODEC design is highly efficient, modular and can be easily combined with a bus partitioning technique. We also investigate the implementation issues and our experimental results show that the proposed CODEC complexity is orders of magnitude better compared to the brute force implementation. Compared to the best existing approaches, we achieve a 17% improvement in logic complexity. A high speed design can be achieved through pipelining.Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008; 01/2008
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ABSTRACT: Abstract A low-voltage and low-power,voltage mode,adder/subtractor using MOSFETs in weak- inversion is presented in this paper. Since the MOSFETs in the proposed circuit are biased in weak inversion, consequently its power dissipation is very low. The proposed circuit has been simulated with the HSPICE using a N-well 0.35μm 2p4m process and the results show that, under the supply voltage of 1V, the power consumption is only 3.32 W and the linearity error is about 3%. Also the 3-dB bandwidth,is about 169 kHz. The proposed circuit is expected to be useful in analog signal-processing and other related applications。 Keywords: weak-inversion、low-power、adder、subtractor。 3