Compact Reduced Order Modeling for Multiple-Port Interconnects
Pu Liu∗, Sheldon X.-D. Tan∗, Bruce McGaughy†, Lifeng Wu†
∗Department of Electrical Engineering, University of California, Riverside, CA 92521
†Cadence Design Systems Inc., San Jose, CA 95134
Abstract— In this paper, we propose an efficient model order
reduction (MOR) algorithm, called MTermMOR, for modeling inter-
connect circuits with large number of external ports. The proposed
method overcomes the difficulty associated with Krylov subspace
based projection MOR methods for reducing circuits with many
ports. The novelty of the proposed method lies on the fact that we
separately compute the poles and residues of each transfer function
in the reduced admittance matrices. Specifically we apply traditional
subspace projection method for computing poles and use hierarchical
symbolic analysis for computing frequency responses of admittances
to determine the residues of transfer functions. In this way, we
only use necessary poles (smaller number of poles) to archive the
same accuracy than subspace projection based methods. Finally
convex programming based optimization is used to enforce the
passivity of the reduced models. The new method can lead to much
smaller reduced models for a given frequency range or much higher
accuracy given the same model sizes than subspace projection based
methods for multi-port interconnect circuits. Experimental results on
several industry interconnect circuits demonstrate the advantage of
the proposed method over the subspace projection based methods.
Compact modeling of passive RLC interconnect circuits by
model order reduction techniques has been intensively studied
in the past due to the urgent need to reduce the increasing
circuit complexity as technology scales.
The most efficient and successful one is based on subspace
projection , , , , , which was pioneered by
Asymptotic Waveform Evaluation (AWE) algorithm  where
explicit moment matching was used to compute dominant
poles at low frequency. Later more numerical stable tech-
niques are proposed , , ,  by using implicit
moment matching and congruence transformation.
One problem with the existing projection based model
order reduction techniques is that they are not efficient to
reduce circuits with many ports. This is reflected in several
aspects of the existing algorithms like PRIMA . First, the
time complexity of PRIMA is proportional to the number
of ports of the circuits as moments excited by every port
need to be computed and matrix-valued transfer functions
are generated. Second, the poles of the reduced models are
linearly increasing with the number of ports, which make the
reduced models much larger than necessary. The fundamental
reason is that all the projection methods are working directly
on the moments which contain the information of both poles
and residues for the corresponding transfer function. To deal
This work is funded by NSF CAREER Award CCF-0448534, UC Micro
#05-111 via Cadence Design System Inc.
with more ports, we have more transfer functions and thus
more poles and residues to compute. However, poles among
different transfer functions are the same for the same circuits
as poles are characteristics of a system. But projection based
methods can’t take advantage of this as they operate directly
on moments. As more residues are computed for more transfer
functions, more poles are also generated. However, generating
more poles does not always help to improve the accuracy
of the reduced models because more block moments are not
always matched as the number of poles increases. As a result,
projection based methods lead to larger reduced models than
necessary when the number of ports are larger.
One way to resolve this problem is by means of port
reductions. Recent work by Feldmann et al
the port dependence to reduce the number of ports under
some error metric constraints. This work however is limited
to circuits with main similar ports and it can’t be applied to
general linear circuits with many independent ports. Another
approach which is also amenable for a circuit with multiple
ports is the hierarchical model order reduction methods ,
. But hierarchical model order reduction is also numeri-
cally unstable except for tree circuits . The improvement
version can produce more accurate models at the expense of
multi frequency point expansions .
In this paper, we proposed a new model order reduction
method that overcomes the difficulty associated with subspace
projection based MOR methods for reducing circuits with
many ports. The basic idea of the proposed method is to sepa-
rately compute the poles and residues of the transfer functions
in the reduced admittance matrices. This can be achieved
firstly by applying traditional subspace projection methods
to compute the poles and then using hierarchical symbolic
analysis for computing frequency responses of admittances
to determine the residues of transfer functions. Since the
traditional projection based MOR is used only for computing
the poles, we only need to compute the poles necessary for the
accuracy requirements. To ensure the passivity of the reduced
model, a convex programming based optimization is applied
finally. Our experimental results show that the new method
can lead to much smaller reduced model sizes for a given
frequency range or much higher accuracy given the same
model sizes than subspace projection based methods.
This paper is organized as the follows: Section II reviews
the Krylov subspace based projection methods and points
out the their weakness for reducing circuit with multiple
ports. Section III will present our new model order reduc-
tion algorithm called MTermMOR, which consists of three
steps. Section IV will present the experimental results, which
demonstrates the advantage of the proposed method over
the projection methods on several real industry interconnect
circuits. The conclusion and future works are presented in
II. REVIEW OF SUBSPACE PROJECTION BASED MOR
In this section, we review the Krylov subspace based
projection methods and point out the their weakness for
reducing circuit with multiple port.
We look at the most representative Krylov subspace
method, PRIMA . Without loss of generality, a linear m-
port electrical circuit can be expressed as
C ˙ xn= −Gxn+ Bum
where x is the vector of state variables and n is the number
of state variables, m is the number of independence sources
specified as ports. C, G and B are matrices from stamping
of circuit devices and L indicates the output port.
Define A = −G−1C, A ∈ ?n×nand R = G−1B,
R = [r0,r1,...,rm] ∈ ?n×m. The y-parameter matrix after
Laplace transformation is Y (s) = LT(G + sC)−1B =
LT(In− sA)−1R where In is the n × n identity matrix.
The block moments of Y (s) are defined as the coefficients
of Taylor expansion of Y (s) around s = 0:
Y (s) = M0+ M1s + M2s2+ ...
where Mi∈ ?m×mand can be computed as Mi= LTAiR
The idea of model order reduction is to find a compact sys-
tem of a much smaller size than the original system. Krylov
subspace based method accomplishes this by projecting the
original system on a special subspace which expands the
same space as the block moments of the original system.
Specifically, the Krylov subspace is defined as
k = ?q/m?,
l = q − km.
For simplicity of expression, we assume q = m×k in the
following. In reality any k can be chosen. Then, PRIMA tries
to find orthogonal matrix X ∈ ?n×qsuch that colsp(X) =
˜C = XTCX
˜B = XTB
˜G = XTGX
˜L = XTL
the reduced system of size q is found as
˜C˙˜ xn= −˜G˜ xn+˜Bum
The reduced systems have q poles, which are the dominant
poles of the original systems. Notice that the order of block
moments k is related to q by k = ?q/m?. To match the
first block moment (k = 1), we need at least m poles. For
every one order of block moment increase, we need to add
additional m poles, which leads a highly inefficient reduction
We use the following practical industry interconnect circuit
from our industry partner to further illustrate this problem.
The circuit has 3 ports and 219 nodes. Fig. 1 shows the
frequency response of one of the nine transfer functions.
With 3 block moments, PRIMA matches the exact response
up to 3GHz fairly well. However, to generate the Krylov
subspace in (5), we need 9 columns, which indicates the
reduced system size is 9, i.e. it has 9 poles. However with
the new method proposed in this paper, we can actually
obtain a reduced system of the same size but matches the
original system response up to 100GHz and still preserves
passivity as PRIMA does. As the number of ports grows,
generating a certain number of block moments becomes more
and more expensive and the reduce system becomes much
larger. However, in real industrial interconnect circuits, sub-
circuits can easily have ten to hundreds ports, and substrates
can even be models with hundreds of ports. For this kind
of circuits, the Krylov subspace projection method will be
Original System with 219 nodes
MtermMOR model with 9 poles
PRIMA model with 9 poles
Fig. 1. Frequency response of 3-input circuit.
III. THE PROPOSED NEW MODEL ORDER REDUCTION
In this section, we present the new model reduction algo-
rithm, which is suitable for circuits with multiple ports.
The key idea of the proposed method is to compute
the poles and residues of the rational admittances (transfer
functions) separately. In this way, we can avoid the generation
of unnecessary poles as done in the traditional subspace
The new method consists of three steps to produce compact
passive models for passive interconnect circuits.
MTermMOR: The New Model Order Reduction
1. Compute the required poles by a subspace projection
2. Compute the frequency responses of all the rational ad-
mittances for the desired frequency ranges by symbolic
3. Apply convex programming based method to find the
residues of each rational admittance and ensure the
passivity of the reduced admittance matrix.
Since the poles and residues are computed separately, we
can only generate required poles which have impacts on the
interested frequency range. As a result, only a few poles are
typically required. In the sequel, we detail each reduction
We want to stress that the new method is different from
the traditional frequency-domain fitting method in that (1)
the poles are computed by projection-based methods which
are the most accurate methods (versus methods like di-
rect moment matching); (2) exact admittance responses are
obtained by hierarchical simulation method which is more
efficient than other numerical methods used in SPICE and
other simulators (versus measured results and other simulated
results); (3) The resulting reduced model is passive.
A. Computation of System Poles By Subspace Projection
For our problem in this step, we are only interested
in the poles of the circuits. The computation costs is no
longer associated with the number of ports as all the transfer
functions among different ports share the same set of poles.
There are several ways to find the required system poles
that are dependent on how the moments are computed in
the subspace projection framework. The simplest way is to
compute the moments from just one input (any one port)
until the sufficient number of moments are obtained. The
second method obtains the moments from different inputs.
If we use the moments from all the m ports, we obtain the
block moments as used in PRIMA. But we may only need a
few orders of block moments as the poles generated will be
km, where k is the order of block moments for the accuracy
After the q moments are generated either from one input or
multiple inputs, the projection method X is generated and the
reduced system is obtained by the congruence transformation
as shown in Eq.(6) and Eq.(7). The required q poles can be
found by the eigen-decomposition on matrix˜G−1˜C, whose
eigenvalues are reciprocals of the required poles:
where piand λiare the ith pole and eigenvalue.
Moreover, by applying the pole selection rule in , we
actually prune out a great portion of poles that have little
impact in the frequency range of interest. Specifically, in
contrast to many analog circuits where most poles carefully
designed to lie on the real axis, the poles of interconnect
circuits are usually complex poles. As shown in , poles
that dominate the transient response in interconnect circuits
are those near the imaginary axis with large residues. And
as observed in , the frequency range that a pole has a
major impact is closely related to its imaginary part: the pole
has peak responses at frequency equaling to the value of its
imaginary part divided by 2π. With these observations we can
eliminate poles that have little impact on the frequency range
of our interest.
Indeed as shown in Fig. 2, we can use only 4 of the 9
poles in a example circuit and still match the exact response
very well. The size of the model system is reduced from
219 to 4 but with very good accuracy as it matches with
the original system up to 100GHz. This example shows that
there exist great potential to further reduce the model sizes
from subspace projection based methods while maintaining
the same or better accuracy.
Original System with 219 nodes
MtermMOR model with 4 poles
PRIMA model with 9 poles
Fig. 2. Frequency response of 3-input circuit.
B. Symbolic Hierarchical Analysis for Admittance Response
Once the poles are computed, we need to compute the
residues of each rational admittance function. For this pro-
pose, we need to know the frequency response of each
rational admittance function in the reduced admittance matrix
Yk×k(s). This can be computed efficiently by using the
symbolic hierarchical analysis . In the following, we
briefly review the hierarchical symbolic analysis first. Then
we compare it with SPICE for frequency domain admittance
For a given circuit formulated in the modified nodal analy-
sis (MNA) as MX = b. It can also be rewritten in the
following form (Schur’s decomposition):
The matrix, MII, is the internal matrix associated with
internal variable vector xI.
Hierarchical reduction is to eliminate all the variables in xI,
and transform (9) into the following reduced set of equations:
where MBB∗= MBB− MBI(MII)−1MIBand bB∗= bB−
MBI(MII)−1bI. Suppose that the number of internal variables
is t, and the number of boundary variables is m. Then each
matrix element in MBB∗and bB∗can be written in the
following expanded forms:
where u,v = 1,...,m and
where u = 1,...,m and Δu,v is the first-order cofactor of
det(M) with respect to au,v.
Symbolic hierarchical analysis is used to represent all
the determinants like det(MII) and first-order cofactor like
nant decision diagram (DDD) based method. It was shown
in , it is as efficient as the direct solution methods such
as LU decomposition methods and scalable to large circuits.
For our problem, we need to compute all the rational admit-
tances in the reduced admittance matrix. For m ports system,
we have m2admittance functions to compute. It turns out
that there are huge advantages of using symbolic hierarchical
method over LU based numerical methods. The reason is
that the cost of computing all the rational admittances are
almost similar to the cost of computing just one rational
admittance due to the symbolic sharing among all the rational
We use the clock net with 219 nodes to illustrate this. Fig. 3
shows the computation costs of the symbolic hierarchical
method versus the SPICE on this circuit with different number
of ports used. Notice that each entry in the admittance
matrix is essentially a transfer function. For example, when
computing frequency response of the (1,2) entry, we need to
apply a voltage source at port 1 and observe the current at
port 2. A lot of information can be reused in our hierarchical
symbolic analysis engine, but SPICE cannot take advantage of
this and we need to change the input and output information
for each of the admittance matrix entry. As a result the
simulation time of SPICE increases linearly with the number
of ports as shown in Fig. 3. But for the hierarchical analysis
the computational cost increase is much smaller and the
difference will become more significant as more ports are
k2symbolically using the determi-
C. Residue Computation and Passivity Enforcement
Passivity is an important property of many physical sys-
tems. Brune  has proved that the admittance and impedance
matrix of an electrical circuit consisting of an interconnection
of a finite number of positive R, positive C, positive L, and
transformers are passive if and only if their rational functions
are positive real.
For a general linear (linearized) time-invariant network, we
describe it in state-space equations as follows.
˙ x = Ax + Bu
y = Cx + Du
Where x is n-dimensional state vector, u is p-dimensional
input vector, and y is q-dimensional output vector. The
Hierarchical Symbolic Analysis
Fig. 3. Comparison of computation cost for admittance.
transfer function through Laplace transformation is
Y (s) = C(sI − A)−1B + D
where I denote an identity matrix with the same dimension
as state matrix A.
In  a Positive Real Lemma has been introduced to check
passivity of the system. The following two statements can be
proved to be equivalent.
(a) a transfer function matrix Y (s) is positive real.
(b) Let (A B C D) be a state-space representation of
Y (s). ∃K,
K = KT,K ≥ 0,
such that the Linear Matrix Inequality (LMI)
If we include the term proportional to s in the transfer
function, which means we would like to know what would
happen in infinite frequency, we can write the admittance
matrix in terms of (A B C D) as
ATK + KA
BTK − C
KB − CT
−D − DT
Y (s) = sY∞+ D + C(sI − A)−1B
In order to keep the transfer function consistently positive
real, the term Y∞must satisfy
Y∞= (Y∞)T, Y∞≥ 0
In summary, the problem of checking whether the ad-
mittance matrix Y (s) is positive real is transferred into the
problem of checking whether its corresponding state space
model in terms of (A B C D Y∞) is positive semi-definite.
It turns out that the latter is more easily to check and enforce
than the former.
After we apply the traditional subspace projection method
for pole computation, we can obtain its state-space repre-
sentation A and B. We assume that all admittance rational
functions share the common poles of the system. Then for a
multi-variable m-port network, we can write its state-space
representation in the controllable form as
. Where each Ap,p∈ ?n×nand Bp,p∈ ?n×1. So the state
matrix A ∈ ?mn×mnand the input matrix B ∈ ?mn×m.
Correspondingly the residues we want to compute can be
Where each Cp,q∈ ?1×n, Dp,q∈ ?1×1.So the output matrix
C ∈ ?m×mnand D ∈ ?m×mas well as Y∞∈ ?m×m.
Using hierarchical symbolic analysis, we get the frequency
responses of admittancesˆY (s) with a set of N sampling
points. LetˆYp,q(sk) be the exact value of the entry (p,q) at the
kthfrequency point and˜Yp,q(sk) be the computational value
obtained from the optimized C, D, Y∞. The optimization
problem is to determine C, D, Y∞such that a cost function
is minimized with constraints on the error (˜Yp,q−ˆYp,q). Here
the constraints are on the weighted least square error, taken
over N frequencies
For simplicity, you can assume that wp,q,k= 1 for all values
of k, p and q. In this paper we choose wp,q,k= 1/?ˆYp,q(sk)?
to normalize the relative error.
Now we can write the whole convex optimization problem
subject to:Eq. (15), (16), (18), (21)
∀1 ≤ p,q ≤ m,tp,q≤ t,t ≥ 0
where m is the port number of the circuit. Both the objective
function and the constraints are convex functions of variables
t, tp,q, K, C, D, and Y∞.
Since N may be large, Eq.(21) will lead to a very large
number of constraints. Thus we use a more compact form 
in our implementation.
IV. EXPERIMENTAL RESULTS
The proposed method has been implemented using C++
and MATLAB. We tested our algorithm on two real industry
interconnect circuits from our industry partner. The experi-
mental results are collected on a PC with P-IV 3.0Ghz CPU
and 512MB RAM.
The convex programming problem is solved by using a
standard optimization package, SeDuMi  in our passivity
enforcement implementation. SeDuMi is powerful software
package add-on for MATLAB, which allows you solve op-
timization problems with linear, quadratic and semi-definite
We use PRIMA as the Krylov subspace projection method
for pole computation implemented in MATLAB. The fre-
quency responses are computed using the symbolic hier-
archical analysis tool. Then the convex programming tool,
SeDuMi, take in the poles and frequency response information
and perform the optimization to produce the final reduced
models in s-domain.
The first interconnect circuit clktree50, is a clock tree
circuit in 160nm technology. This network contains 210 nodes
and 9 terminals.
In Fig.4, the PRIMA model’s response is accurate at the
frequency no more than 15GHz. However the MTermMOR
model’s response matches the original circuit up to 50GHz.
Moreover the MTermMOR model only contains 5 dominant
poles comparing with 90 poles in PRIMA model.
Fig. 4. Frequency response comparison among the original circuit, PRIMA
model, and MTermMOR model of the circuit clktree50.
The similar results are obtained from another example
sram1026, which is one bit line circuit from a SRAM circuit
also in 160nm technology. This circuit includes 516 nodes, 6
inputs and 256 outputs.
Due to the large number of terminals, the constraints
Eq.(21) will be increased quadratically, which will also
increase the computational cost to solve the optimization
problem Eq.(22). However this problem can be mitigated by
using recently introduced terminal reduction technique 
before we perform the convex program. After the terminal
reduction, the 6 input ports are all kept and the output
ports are reduced to 5 comparing with the original 256
output terminals. Then the convex programming algorithm
can easily handle the terminal reduced circuit, which has only
The experimental result is shown in Fig.5. PRIMA’s model
by using 44 poles is accurate up to 2Ghz while the MTer-
mMOR model matches the original circuit’s response up to
10Ghz with just 4 poles. Both examples clearly demonstrate
the advantage of the proposed method.
We also realize this reduced model into an equivalent
SPICE netlist and compare its step response with that of the