Conference Paper

Design Methodology of Low Power JPEG2000 Codec Exploiting Dual Voltage Scaling

Dept. of Electron. Eng., Tsinghua Univ., Beijing
DOI: 10.1109/ICASIC.2005.1611280 Conference: ASIC, 2005. ASICON 2005. 6th International Conference On, Volume: 1
Source: IEEE Xplore

ABSTRACT This paper proposed a novel dual voltage scaling layout architecture and a design methodology of low power JPEG2000 codec exploiting dual voltage scaling. Fabricated in SMIC 0.18mum 1P6M standard CMOS technology, this codec is capable of JPEG2000 compression/decompression with a 1280times1024 pixel (YUV422 full color) at 20 frames/s employing 100MHz operation frequency. And the power consumption is 465mW @ 1.8V and 100MH. Applied with dual voltage scaling technique, the power dissipation is reduced by 28.5%

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