Conference Paper

Integration of Cu and extra low-k dielectric (k=2.5∼2.2) for 65/45/32nm generations

Adv. Module Technol. Div., Taiwan Semicond. Manuf. Co., Hsin-Chu, Taiwan
DOI: 10.1109/IEDM.2005.1609273 Conference: Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International
Source: IEEE Xplore


This paper investigated various approaches to integrate Cu and extra low-k dielectric (ELK, k=2.5∼2.2) for dual damascene fabrication. We demonstrate a trench-first hard mask process flow without k degradation by ash-free process and a novel pore sealing technique. In addition, we have extended this pore sealing concept to a via-first PR mask approach for porous ELK of 2.2. Both optimized hard mask and PR mask process flows are demonstrated promising for Cu/ELK integration for 65/45/32nm generations.

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