This paper presents the design and study of circuit architecture able to perform 16 Gbps GFP frame delineation with single bit error correction using UMC 130 nm standard cell technology. The design targets the development of a hard macro core for the design of next generation network processing platforms.
[Show abstract][Hide abstract] ABSTRACT: Framing protocols employ cyclic redundancy check (CRC) to detect errors incurred during transmission. Generally whole frame is protected using CRC and upon detection of error, retransmission is requested. But certain protocols demand for single bit error correction capabilities for the header part of the frame, which often plays an important role in receiver synchronization. At a speed of 10 Gbps, header error correction implementation in hardware can be a bottleneck. This work presents a hardware efficient way of implementing CRC-16 over 16 bits of data, multiple bit error detection and single bit error correction on FPGA device.
Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on; 01/2005
[Show abstract][Hide abstract] ABSTRACT: The use of VLSI technology to speed up cyclic redundancy checking
(CRC) circuits used for error detection in telecommunications systems is
investigated. By generalizing the analysis of a parallel prototype,
performance is estimated over a wide range of external constraints and
design choices. It is shown that parallel architectures fall somewhat
short of ideal speedups in practice, but they should still enable
current CMOS technologies to go well beyond 1 Gb/s data rates
IEEE Transactions on Communications 05/1992; DOI:10.1109/26.141415 · 1.99 Impact Factor
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