Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology

Abstract

With technology scaling, elevated temperatures caused by increased power density create a critical bottleneck modulating the circuit operation. With the advent of FinFET technologies, cooling of a circuit is becoming a bigger challenge because of the thick buried oxide inhibiting the heat flow to the heat sink and confined ultra-thin channel increasing the thermal resistivity. In this work, we propose compact thermal models to predict the temperature rise in FinFET structures. We develop cell-level compact thermal models for standard INV, NAND and NOR gates accounting for the heat transfer across the six faces of a cell. Temperature maps of benchmark circuits exhibit close correspondence with dynamic power maps because of confined regions of heat generation separated by low thermal conductivity material. It is illustrated that temperature-aware timing analysis is imperative, because of high inter-cell temperature gradient. Accurate prediction of temperature in the early phase of design cycle gives valuable estimation of power/performance/reliability of a circuit block and guides in the design of more robust circuits.

Full text

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Compact Thermal Models for Estimation of Temperature-dependent
Power/Performance in FinFET Technology
Aditya Bansal, Mesut Meterelliyoz, Siddharth Singh*, Jung Hwan Choi, Jayathi Murthy§, Kaushik Roy
School of Electrical and Computer Engineering, Purdue University,
§Department of Mechanical Engineering, Purdue University
West Lafayette, IN 47907
*Department of Electrical Engineering, Osmania University, India
Email: {bansal, mesut, choi56, jmurthy, kaushik}@purdue.edu
Abstract: With technology scaling, elevated temperatures
caused by increased power density create a critical bottleneck
modulating the circuit operation. With the advent of FinFET
technologies, cooling of a circuit is becoming a bigger challenge
because of the thick buried oxide inhibiting the heat flow to the
heat sink and confined ultra-thin channel increasing the thermal
resistivity. In this work, we propose compact thermal models to
predict the temperature rise in FinFET structures. We develop
cell-level compact thermal models for standard INV, NAND and
NOR gates accounting for the heat transfer across the six faces
of a cell. Temperature maps of benchmark circuits exhibit close
correspondence with dynamic power maps because of confined
regions of heat generation separated
conductivity material. It is illustrated that temperature-aware
timing analysis is imperative, because of high inter-cell
temperature gradient. Accurate prediction of temperature in the
early phase of design cycle will give valuable estimation of
power/performance/reliability of a circuit block and will guide in
the design of more robust circuits.
by low thermal
I. Introduction
The need for higher performance in smaller area has
always been the driving force for the semiconductor industry.
Aggressive technology scaling has led to increase in transistor
density on a chip and innovative device structures (UTB-SOI,
FinFET, Tri-gate etc.) to achieve the desired performance.
Increasing packing density has led to power density to
become a critical bottleneck in the design of microelectronics.
The local temperature rise can result in circuit malfunction
and can also impact performance, power and reliability. For
every 10°C increase in temperature, a MOSFET’s drive
current decreases approximately 4% and interconnect
(Elmore) delay increases approximately 5% [1]. To avoid the
increase in temperature (or to dissipate heat), a heat sink is
integrated on the chip package. However, since the heat sink
is away from the device layer, it is not very efficient in taking
the heat directly away from the transistors.
Several architecture and circuit level techniques have
been proposed to distribute the temperature uniformly over
the chip and reduce the hot spots. At architecture level,
several dynamic thermal management (DTM) schemes have
been proposed including dynamic voltage scaling (DVS) [2],
discrete frequency scaling (DFS), migrating computation
(MC) [3] and dynamic clock throttling (DCT) [4] etc. These
techniques depend on the accurate thermal modeling of
circuit blocks. Conventionally, circuit blocks are modeled as
heat sources with uniform temperature distribution inside the
block. There are several thermal models available in the
literature at different stages of design cycle of VLSI circuits.
For example, a dynamic compact thermal
microarchitecture level is presented in [3]. Grid-like thermal
models for temperature-aware-design at arbitrary granularities
are presented in [5]. Weiping et al. [6] modeled the
dependence of power and performance on the temperature at
microarchitecture level. However, thermal modeling at finer
granularity level i.e., transistor level or logic gate level is
required for more accurate estimation of local hot spots.
The increasing thermal problems are more aggravated in
next generation transistor technologies such as Ultra-thin-
body (UTB) Silicon-On-Insulator (SOI) MOSFETs and
FinFETs. FinFETs have gate insulator all around the channel
where heat is generated. This oxide layer results in less
efficient dissipation of heat compared to bulk-MOSFETs
where heat mainly dissipates through the substrate [7]. Eric et
al. [8] [9] discuss the impact of confined dimensions and
complicated geometries on self-heating in these devices.
Ultra-thin silicon body improves the device scalability by
reducing short-channel-effect, higher on-current and near
ideal sub-threshold slope. However, the thermal resistivity of
the thin active region is higher compared to thick active
region in bulk-MOSFETs. Also, because of increased surface
model at
Fig. 1: Schematics of bulk-Si MOSFET and FinFET. In
FinFET, gate surrounds the channel which is separated
from the bulk-Si by thick BOX.

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to volume ratio in UTB-SOI devices, thermal boundary
resistances of various materials’ further impede the heat flow
[9]. Fig.1 shows the schematics of bulk- MOSFET and
FinFET devices. In bulk-MOSFETs, heat generated in device
layer as well as interconnect layers is mainly dissipated
through the heat sink integrated with bulk substrate silicon.
However, in FinFETs, device layer is separated from bulk-Si
substrate by thick buried oxide layer (which has two orders of
magnitude lower thermal conductivity than silicon [10]).
Therefore, heat dissipation is mainly through the contact
holes and interconnects. This elevates the local temperature
rise in FinFET circuits. Because of temperature dependence
of critical electrical parameters, it is becoming increasingly
clear that electro-thermal co-design of transistors and circuits
is necessary to arrive at optimal power and performance.
However, a typical chip may have hundreds of millions of
transistors, and a direct thermal simulation of such a
collection of devices is all but impossible with current
computing power. Instead, in this paper, we develop compact
thermal models for circuit components used in cell-level
electrical models in circuit design. Detailed computational
models for three cell-level components – NAND, NOR and
INV – are created based on Fourier theory.
Fig. 2 shows the design flow adopted in this work for the
estimation of temperature-dependent power/performance/
reliability in FinFET based circuits. Compact thermal models
are generated for standard cell layouts. The temperature
information for each standard cell is associated with its heat
generation and heat flow across the boundaries to the
neighboring cells. Note that temperature of a cell is dependent
on the heat generation in the transistors and temperatures of
neighboring cells. Hence, real temperature can not be
determined till a floorplan is generated. These models are
used in generating the temperature profile of a circuit for a
given floorplan. Wiring capacitance is accounted for as
lumped capacitive load at the output of driving gate. The
temperature map is used to estimate the increase in power
dissipation,deterioration in performance and lifetime
reliability because of self-heating and local temperature rise.
This estimation can be primarily used in two ways for robust
circuit design: (1) It can be used to define an appropriate cost
function to develop thermally-aware placement and
optimization strategies for VLSI circuits, (2) Temperature
map can be used for better delay analysis of the critical paths
in early phase of the design cycle.
In this work, we are targeting the problem of heat
dissipation in predictive28nm ITRS [11] specified
technology node for FinFET circuits. In section 2, we discuss
the impact of local temperature rise on the power and
performance of the standard cells. In section 3, we develop
the compact thermal models for standard logic cells designed
using NMOS and PMOS FinFETs. The joule heating in
devices is simulated for the worst case input pattern (each
transistor switching at every clock cycle) using Taurus
Device Simulator [12]. Switching activity dependent
temperature rise in a standard cell is modeled based on three-
dimensional thermal resistances of the cell. In section 4, we
generate the temperature maps of benchmark circuits and
discuss the local temperature rise in FinFET circuits followed
by conclusions in section 5.
Design Design
(VHDL/Verilog)(VHDL/Verilog)
Logic SynthesisLogic Synthesis
Block Partitioning/
Floorplanning Floorplanning
Thermal mapThermal map
Delay/Timing
AnalysisAnalysis
FinFET standard
cells’ layoutcells’ layout
Thermal ModelsThermal Models
Activity, wiring
capacitance, power
etc. informationetc. information
Power
EstimationEstimation
ReliabilityReliability
Block Partitioning/
Delay/Timing
FinFET standard
Activity, wiring
capacitance, power
Power
Fig. 2: Design flow for temperature based power/
performance/reliability estimation.
II. Performance and Power Estimation
The temperature rise in a transistor affects its electrical
characteristics. Mobility and sub-threshold slope degrade
with the increase in temperature resulting in reduced on-
current and hence, increased delay. Also, static leakage
increases with temperature because of increase in sub-
threshold leakage. In scaled technology generations, the static
power is becoming a significant component of the total power
dissipation, especially in the low activity sections of a chip
like memory. Moreover, reliability is strongly dependent on
the temperature. Increasing the temperature exponentially
decreases the lifetime of a circuit. A first order model of
mean-time-to-failure (MTF) can be given by Arrhenius
equation:
MTF = MTF0 exp(Ea/kBT)
exhibiting the exponential deterioration in reliability with
temperature. We quantitatively analyze the temperature
dependence of delay and power in a 2-input NOR gate.
Similar analysis has been done for INV and 2-input NAND
gates, however, results are omitted for brevity.
(1)
A. Delay dependence on temperature
With the increase in temperature, mobility degrades in
transistors. This effect is more dominant in bulk MOSFETs
because of heavily doped body used to reduce short-channel-
effect. However, in fully-depleted double gate SOI devices,
body is left undoped resulting in less deterioration of mobility
with temperature. Mobility degradation reduces on-current,
however, with increase in temperature, threshold voltage
decreases resulting in improved on-current. These two effects
counter each other and the net variation in on-current is
dependent on the relative sensitivities of mobility and
threshold voltage to the temperature. To analyze the impact of
temperature on the intrinsic delay, we simulated a three NOR
stage ring oscillator with inputs of each NOR gate tied
together. Fig. 3 shows the intrinsic delay increase with
temperature. It can be seen that intrinsic delay increases

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approximately 20% for 120°C rise in cell temperature. This
increase in intrinsic delay coupled with increase in Elmore
delay of interconnects because of increased electrical
resistivity can pose serious challenges to circuit designers
demanding more rigorous timing analysis. One more
observation is the decrease in output swing (Fig. 3) because
of increase in sub-threshold slope and reduced Ion/Ioff ratio.
Output swing decreases 9% for 120°C rise in temperature.
This will result in reduced noise margins in cascaded logic
gates at high temperatures.
B. Power dependence on temperature
Power dissipation in a circuit depends on its operating
mode and can be given by
PP
?
Static power dissipation (Pstatic) is due to the leakage
currents – sub-threshold leakage, gate direct tunneling
leakage and reverse-biased junction band-to-band tunneling
leakage – in off-state of a transistor [13]. Sub-threshold
totalstatic dynamic
P
?
(2)
leakage increases exponentially with the decrease in threshold
voltage and is given by,
( ) /
q VV mk T
gstB
II e
?
/
(1)
ds B
qVk T
subo
e
?
?
?
(3)
This results in 12X increase in static leakage for the
temperature rise of 120°C in a NOR gate (Fig. 4).
Dynamic power dissipation (Pdynamic) is mainly due to:
(1) charging/discharging of the capacitances at the
output and internal nodes of a cell (Pcap,dyn).
(2) short-circuit power due to direct current path
between the power supply and ground (Psc,dyn).
The switching of the capacitances at the output and
internal nodes of a cell depends on the input pattern. Average
dynamic power dissipation can be obtained by considering
the average number of transitions per clock cycle. The
dynamic power can be given by,
?
,
0.5
cap dynDD
PVfC
????
?
?
where, VDD is the supply voltage and f is the clock frequency.
Cload includes the output load capacitance and the device
capacitances of transistors connected at the output node and
?out is the average number of output transitions in a clock
cycle. Ci is the internal node capacitance of the ith node and ?i
is the average number of switching transitions per clock cycle
at the ith node.
Short-circuit power is due to direct path of current flow
between the power supply and ground during output
transition. Because of the non-zero rise/fall times of an input
signal, pull-down and pull-up networks can be simultaneously
conducting in a CMOS circuit resulting in a direct current
path between power supply and ground. With the increase in
temperature, sub-threshold slope of the transistors increases
and Ion/Ioff ratio decreases. This results in increased short
circuit power. Fig. 4 shows the dynamic and static power
dissipation in a NOR gate. Dynamic power dissipation is
calculated by integrating the currents in a 3-stage ring
oscillator. It can be seen that dynamic power dissipation
slightly increases with temperature mainly because of
increase in short-circuit power.
204060 80 100 12014
0.9
0.95
1
1.05
1.1
1.15
1.2
1.25
Temperature (deg. Celsius)
Normalized delay and output
Normalized Delay
Normalized Output
Fig. 3: Normalized delay and output swing of 3 NOR
stage ring oscillator with temperature.
?
2
()
load outii
C
??
??
?
?
???
?
(4)
2060 100140
0
0.5
1
1.5
2
2.5x 10
−5
Temperature (deg. Celsius)
Total Power (Watts)
Static
Dynamic
Fig. 4: Total power dissipation in NOR cell with
temperature.
III. Compact Thermal Models
A. Detailed Component Model
Detailed computational models for three cell-level
components – NAND, NOR and INV are created based on
Fourier theory. A typical NOR gate structure is shown in Fig.
5, including two PMOS and two NMOS FinFETs at the 28
nm node. The gates and fins are also shown. The simulation
includes portions of the metallic contacts, but not all the
metallization layers. These structures are enclosed in a
domain of size 504 nm x 300 nm x 539 nm and are located on
the y=150 nm plane. The rest of the interior volume is filled
with SiO2. In this orientation, the metallization layers would
lie above the y=300 nm boundary, while the heat sink would
lie below the y=0 boundary. Other details for the three
components are shown in Table 1. The gate material is
assumed to be aluminum, as are the metallic contacts, and

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standard temperature-independent thermal properties for bulk
Si, SiO2and aluminum are assumed.
The volumetric heat generation due to self-heating is
computed using the TAURUS device simulator [12].
electrical simulation is 2D, in the x-z plane in Fig. 5, and
yields the heat source J.E (x, z) for a typical fin in the PMOS
or NMOS device. Thermal transport in the geometry is
necessarily 3D with the primary direction for heat transfer
being perpendicular to the x-z plane. The spatial (x, z)
distribution of the heat generation is assumed to hold
throughout the y-depth of the fins. The FLUENT CFD
software [14] is used to compute the temperature field using
the unstructured mesh technique described in [15].
The
B. Compact Model Generation
The generation of the compact model exploits the fact
that the Fourier conduction equation with constant thermal
properties is a linear elliptic boundary value problem. Thus,
the temperature at any location (x1, y1, z1), or indeed, the
average temperature of the domain, can be uniquely written
as:
???
11111
1
f
?
where the coefficients af are unique to the spatial location
(x1 ,y1,z1), and determine the influence of the six boundary
temperatures of the cuboidal domain on T(x1, y1, z1). The
coefficient a0quantifies the influence of the heat generation
rate q for a given activity ?. The coefficients af have the
property:
6
a
?
Fig. 5: Temperature field in NOR gate on the y=150 nm
plane. Two PMOS and two NMOS FinFETs at the 28 nm
technology node are shown. Heat generation in the
fingers causes a temperature rise of 39°C above ambient.
???
6
10111
,,,,,,
ff
T x y zax y z Tax y zq
???
?
(5)
1
1
f
f
?
?
(6)
By the same token, the heat transfer rates qbjout of each
of the six boundaries of the domain may also be written as:
6
q b Tb
?
For a given geometry, materials properties, and spatial
pattern of heat generation, the coefficients af, a0, bfj and b0j are
uniquely determined, and constitute the compact model of the
NOR, NAND or INV component. Seven temperature
calculations are done using seven different sets of boundary
temperatures to obtain a total of seven coefficient values (six
af’s and a0). The same seven runs are also sufficient to
determine seven values (bfj and b0j) for each of the six
boundary face heat transfer rates qbj, j=1,2,…6 . A typical
compact model for a NOR gate is present in Table 2. Here,
the average component temperature is related to the six
boundary temperatures of the computational domain and the
heat generation rate; similarly, the heat transfer rates at the six
boundary faces. This compact model will recover exactly the
same average temperature and boundary heat transfer as the
detailed model for any set of Dirichlet boundary conditions
on the boundaries.
0
1
j=1,2,...6
bj fjfj
?
f
q
??
?
(7)
Table I: Parameters for Thermal Simulations
Comp-
onent
DevicesDomain
Size
Mesh
Size
(Hexah-
edra)
267,376
Number of
Fins
Heat Generation
Per Fin
(W)
Net Heat
Generation
in Device
(W)
2.0326x10-4
NOR2 PMOS,
2 NMOS
504 nm x
300 nm x
539 nm
PMOS1 : 4
PMOS2: 4
NMOS1: 1
NMOS2: 1
PMOS1 : 2
PMOS2: 2
NMOS1: 2
NMOS2: 2
PMOS1 : 2
NMOS1: 1
PMOS1 : 4.4399x10-6
PMOS2: 5.211x10-6
NMOS1: 8.2332x10-5
NMOS2: 8.2332x10-5
PMOS1 : 3.1178x10-5
PMOS2: 2.1156x10-5
NMOS1: 8.4242x10-6
NMOS2: 8.4242x10-6
PMOS1 : 9.496x10-7
NMOS1: 3.4595x10-6
NAND2 NMOS
2 PMOS
504 nm x
300 nm x
406 nm
146,260 1.3836x10-4
INV 1 PMOS
1 NMOS
336 nm x
300 nm x
399 nm
228,214
5.3589x10-6

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Table II: Compact thermal model for NOR gate
Tavg =0.1258Tleft + 0.1256Tright+0.2326Tbottom +0.2747Ttop + 0.1228Tback + 0.1185Tfront + 3.5039x104?q
qleft = 7.2206x10-6Tleft -6.8573x10-8 Tright -2.2603x10-6 Tbottom -2.5307x10-6 Ttop -1.1725x10-6 Tback
-1.1885x10-6 Tfront -0.1141 ?q
qright = -6.8573x10-8Tleft +7.2188x10-6 Tright -2.2603x10-6 Tbottom -2.5301x10-6 Ttop -1.1719x10-6 Tback
-1.1879x10-6 Tfront -0.1119 ?q
qbottom = -2.2603x10-6Tleft -2.2603x10-6 Tright +9.2783x10-6Tbottom -5.0752x10-7 Ttop -2.0967x10-6 Tback
-2.1534x10-6 Tfront -0.1168 ?q
qtop = -2.5307x10-6Tleft -2.5301x10-6 Tright -5.0752x10-7 Tbottom +1.0289x10-5 Ttop -2.3629x10-6 Tback
-2.3574x10-6 Tfront -0.3877 ?q
qback = -1.1725x10-6Tleft -1.1719x10-6 Tright -2.0967x10-6 Tbottom -2.3629x10-6 Ttop +6.9145x10-6 Tback
-1.1047x10-7 Tfront -0.1264 ?q
qfront = -1.1885x10-6Tleft -1.1879x10-6 Tright -2.1534x10-6 Tbottom -2.3574x10-6 Ttop -1.1047x10-7 Tback
+6.9977x10-6Tfront -0.1430 ?q
Left (x=0); right (x=xmax); bottom(y=0); top (y=ymax); back (z=0); front ( z=zmax)
IV. Results and Discussions
Once the average temperature and boundary heat transfer
dependence of a logic cell on the boundary temperatures of
the cuboid are known, the next step is cell placement and the
generation of the thermal map of a circuit block. Though the
primary heat flow direction is perpendicular to the plane in
which the logic cells are placed, there is sufficient in-plane
thermal non-uniformity that the thermal transport in all three
coordinate directions must be considered. The logic cells are
arranged in planar mesh of cuboidal cells, with those cells not
containing logic elements assumed to contain SiO2.
Convective heat transfer boundary conditions are posed on all
external boundaries, with the heat transfer coefficients being
chosen to correctly model the thermal resistance due to
metallization layers, the wafer, as well as lateral losses to
other circuit blocks. By enforcing continuity of heat transfer
rate at logic cell cuboid faces, equations for the face
temperatures are found. These, in turn, are used to evaluate
the average logic cell temperature. Heat generation and hence
local temperature rise in a cell depends on the input data
pattern. Therefore, to obtain the worst cast temperature map,
an exhaustive set of test patterns need to be applied. However,
to reduce the computational complexity, we obtain the
average switching activity of each cell in a circuit block for a
large set of random input patterns.
Fig. 6 shows the dynamic power and temperature
distribution in the layouts of alu4 and x3 (MCNC’91 [16])
benchmark circuits. Circuits have been modified to use
standard cells. Floorplans are generated to arrange cells in a
planar grid of 30x30. Each cell volume is either occupied by a
standard cell – NAND, NOR, INV – or filled with SiO2
insulator. The maximum temperature difference inside the
circuit blocks is 20°C. It can be seen that in FinFET based
circuits, the temperature distribution closely corresponds to
the dynamic power map (Fig.6), unlike bulk MOSFETs
where hot spot region distributes over several cells. This is
attributed to the confined silicon channels and lack of
common high conductivity bulk silicon under the device layer.
In FinFET circuits, lateral heat flow is mainly through
interconnects because of the lack of common low thermal
resistivity substrate. This can result in large temperature
differences between the neighboring cells. Power and ground
lines shared by the adjacent cells help in heat flow and
temperature distribution to some extent. Because of high
inter-cell temperature gradients, it’s imperative to perform
temperature-dependent timing analysis at the granularity of
gate level in FinFET circuits. With this estimation, some
circuit level techniques, such as sizing, can be employed to
prevent the failures.
V. Conclusions
In this work, we propose gate level compact thermal
models for estimating temperature rise in FinFET circuits.
The effect of low thermal conductivity buried oxide, confined
ultra-thin channel and thermal boundary resistances of
different materials’ on temperature rise is taken into account.
The floorplans of benchmark circuits show close
correspondence between the temperature maps and dynamic
power maps. This can be attributed to the confined channels
where heat is generated and lack of high thermal conductivity
material (bulk silicon) under the device layer impeding the
lateral heat distribution. Results show that 120°C rise in
temperature can result in 20% increase in intrinsic delay of a
2-input NOR gate and 12X increase in leakage power
dissipation. The proposed thermal models can be used in
estimating temperature rise in early phase of design cycle for
proper timing analysis. The models can also be integrated in
floorplanning algorithms to remove hot spots.
References
[1] C.-H. Tsai et al., “Standard Cell Placement for Even On-Chip
Thermal Distribution,” Proc. of Int. Sym. on Phys. Design,
1999, pp. 179-184.
[2] D. Brooks et al., “Dynamic Thermal Management for High-
Performance Microprocessors,” Proc. 7th Int. Sym. High-Perf.
Comp. Arch., 2001, pp. 171-182.