Enhanced launch-off-capture transition fault testing

Abstract

A novel scan-based at-speed test is proposed in which a transition can be launched either from the scan path or the functional path. The technique improves the controllability of transition fault testing and it does not require the scan enable to change at-speed. The scan enable control information is encapsulated in the test data and transferred during the scan operation to generate the local scan enable signals during the launch and capture cycle. A new scan cell, referred to as local scan enable generator (LSEG), is inserted in the scan chains to generate the local scan enable signals. The proposed technique is robust, practice-oriented and suitable for designs targeted for very low cost ATEs

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Enhanced Launch-Off-Capture Transition Fault Testing
Nisar Ahmed1, Mohammad Tehranipoor2, C.P. Ravikumar1
1ASIC Product Development Center, Texas Instruments India,
2Dept. of CSEE, Univ. of Maryland Baltimore County, tehrani@umbc.edu
?n-ahmed2,ravikumar@ti.com
?
ABSTRACT
With today’s design size in millions of gates and working fre-
quency in gigahertz range, timing-related defects are high pro-
portion of the total chip defects and at-speed test is crucial.
The transition fault model is widely used for detecting delay-
induced defects. There are two transition fault pattern genera-
tionmethods;i.e. launch-off-shift(LOS)andlaunch-off-capture
(LOC). In LOS, the transition is launched during the last shift
cycle from the scan path (non-functional). The scan enable
(SEN) is high during the last shift and must go low to enable
response capture during the capture cycle. The time period for
SEN to make this transition corresponds to the functional fre-
quency. This is not applicable for very low cost ATE, which
have a limitation of one at-speed signal port. In LOC method,
the at-speed constraint on the SEN signal is relaxed and the
transition is launched from the functional path. The controlla-
bility of launching a transition at the target gate is less as it
depends on the functional response of the circuit under test to
the initialization vector.
A novel scan-basedat-speed test is proposedin which a tran-
sition can be launched either from the scan path or the func-
tional path. The technique improves the controllability of tran-
sition fault testing and it does not require the scan enable to
changeat-speed. The scanenablecontrolinformationis encap-
sulated in the test data and transferred during the scan opera-
tion to generate the local scan enable signals during the launch
and capture cycle. A new scan cell, referred to as local scan
enable generator (LSEG), is inserted in the scan chains to gen-
erate the local scan enable signals. The proposed technique is
robust, practice-oriented and suitable for designs targeted for
very low cost ATEs.
I. INTRODUCTION
The semiconductor industry is adopting new fabrication pro-
cesses to meet the area, power and performance requirements.
As a result, modern ICs are growing more complex in terms of
gate count and operating frequency [1]. The deep-submicron
(DSM) effects are becoming more prominent with shrinking
technology,thereby increasing the probabilityof timing-related
defects [2] [3]. For DSM designs, the stuck-at fault test alone
cannot ensure high quality level of chips. In the past, functional
patterns were used for at-speed test. However, functional test-
ing is not a viable solution because of the difficulty and time
to generate these tests for complex designs with very high gate
density. Moreover, the number of required patterns to achieve
high fault coverage can be extremely high for modern designs.
Therefore, more robust at-speed techniques are required as the
number of timing-related defects is growing and effectiveness
of functional and IDDQtesting is reducing [4] [5].
The transition fault and path delay fault testing together pro-
vide a relatively good coverage for delay-induced defects [6]
[7]. Path delay model targets the cumulative delay through the
entire list of gates in a pre-defined path while the transition
fault model targets each gate output in the design for a slow-to-
rise and slow-to-fall delay fault [8]. Transition fault testing is
widely practiced in industry due mainly to its manageable fault
count (two faults in each gate) and availability of commercial
tools. Totest atransitionfault,apatternfirstis appliedtoinitial-
izethecircuitandanotherpatternis appliedto applyatransition
at a target gate terminal. The response is observed at the out-
puts of the circuit under test (CUT). Scan-based structural tests
generated by an automatic test pattern generator (ATPG) are
increasingly used as a cost-effective alternative to the at-speed
functional pattern approach [5] [9].
To perform a scan-based transition fault test, a pattern pair
?V1
termedas the initializationpattern andV2 as the launch pattern.
V2launchesthe signaltransition(0
node. It also helps propagate the output transition to the output
of CUT (scan flip-flops or primary outputs). The response of
the CUT to the patternV2 must be captured at functional speed
(rated clock period). The whole operation can be divided into
3 cycles: 1) Initialization Cycle (IC), where the CUT is initial-
ized to a particular state (V1 is applied), 2) Launch Cycle (LC),
where a transition is launched at the target gate terminal (V2
is applied) and 3) Capture Cycle (CC), where the transition is
propagated and captured at an observable point.
Variousscan-basedtransitionfault testing methods were pro-
posed in literature [10] [11] [12]. Depending on how the tran-
sition is launched and captured, there are three transition fault
pattern generation methods called launch-off-shift, launch-off-
capture, and enhanced-scan.
In the first method,referredto as launch-off-shift(LOS) [10],
the transition at the gate output is launched in the last shift cy-
cle during the shift operation. Figure 1(a) shows the path of
transitionlaunchin LOS methodfora multiplexed-DFFdesign;
similar approach can be applied to an LSSD. The transition is
launched from the scan-in pin (SD) of any flip-flop in the scan
chain. This activates the required transition at the target gate
terminal which is propagated and captured through the func-
tional path at an observable point (D) of any flip-flop in the
scan chain.
Figure 1(b) shows the waveforms during the different cycles
of LOS operation. The LC is a part of the shift operation and is
? V2
? is applied to the circuit-under-test.Pattern V1 is
?
1 or1
?
0)at thedesired
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D
SD
Q
SEN
CLK
Scan−in pattern i
Scan−out response i−1
Scan−in pattern i+1
Scan−out response i
CCLC IC
SEN
CLK
(b)
tf
COMBO LOGIC
(a)
Figure 1. Launch-off-shift Transition Delay Fault Pattern Generation.
D
SD
Q
SEN
CLK
Scan−in pattern i
Scan−out response i−1
Scan−in pattern i+1
Scan−out response i
CCLC IC
CLK
SEN
(b)
tf
COMBO LOGIC
(a)
Figure 2. Launch-off-capture Transition Delay Fault Pattern Generation.
immediately followed by a fast capture pulse. The scan enable
(SEN) signal is high during the last shift and must go low to
capture the response at the CC clock egde. The time period for
SEN to make this 1
0 transitioncorrespondsto the functional
frequency. Hence, LOS requires the SEN signal to be timing
critical. Skewing the clock (CLK) creates a higher launch-to-
capture clock frequency than standard shift clock frequency.
Saxena et al. [13] list more launch-off-shift approaches.
Figure 2(a) shows the transition launch path of the second
approach,referredto as launch-off-capture(LOC) method[11].
In this method, the transition is launched and captured through
the functional pin (D) of any flip-flop in the scan chain. Since,
the launch pattern V2 depends on the functional response of
the initialization vector V1, the launch path is less controllable
due to which the test coverage is low. Figure 2(b) shows the
waveforms of the LOC method in which the launch cycle is
separated from the shift operation. At the end of scan-in (shift
mode), pattern V1 is applied and CUT is set to an initialized
state. A pair of at-speed clock pulses is applied to launch and
capture the transition at the target gate terminal. This relaxes
the at-speed constraint on the SEN signal and dead cycles are
?
added after the last shift to provide enough time for the SEN
signal to settle low.
The third technique, known as enhanced scan [12] requires
that two vectors V1 and V2 are shifted into the scan flip-flops
simultaneously. The main advantage of this technique is that it
simplifies ATPG and offers better coverage for both LOC and
LOS techniques, since it eliminates any dependency between
V2 andV1. Enhancedscan can also have a beneficial impact on
test datavolume,sincemorecompacttest patternscanbegener-
ated. The drawback on enhanced scan is that it needs hold-scan
flops and is area-intensive, making it unattractive for ASIC de-
signs. Enhanced scan using hold-scan flops has been used in
high-performance microprocessors where the area overhead of
the technique is justified.
The LOS method is preferable from ATPG complexity and
pattern count view points when compared to LOC method. In
case of LOC, a high fault coverage cannot be guaranteed due
to the correlation between the two patterns, V1 and V2. As
the design size increases, the SEN fanout exceeds any other net
in the design. The LOS constraints SEN to be timing critical
which makes it difficult to implement using low cost testers and
on designs where the turn-around-time is critical [15]. That is
the main reason that LOC method has been widely practiced,
especially on low cost testers [9]. Note that no at-speed SEN
signal is required for LOC method.
Techniques are required to improve the LOC method’s fault
coverage. In this paper, we propose a technique to improve
the fault coverage and reduce the pattern count by using an en-
hanced LOC technique. It intelligently selects a subset of scan
cells to be controlled by LOC technique and the rest as scan-
path. This improves the controllability of scan cells and detects
some of the hard-to-detect-by-LOCfaults.
Several techniques have been proposed to improve the LOS
fault coverage but there has not been much work on the LOC
method to the best of our knowledge. In [14], a hybrid scan ar-
chitecture is proposed which controls a small subset of selected
scan cells by LOS and the rest are controlledby LOC approach.
A fast scan enable signal generatoris designedwhich drivesthe
LOS controlled scan flops. The ATPG method used is com-
plex and current commercial tools do not support such a tech-
nique. Moreover, the selection criteria of the LOS-controlled
scan flops determines the effectiveness of the method. In some
cases, the number of patterns generated by the hybrid method
exceeds the LOC pattern count.
The implementation of LOS method using low cost testers is
presented in [15]. A local at-speed scan enable signal is gener-
ated using a slow enable signal generated by a low cost tester.
A local scan enable generator is designed; it can be inserted
anywhere in scan chain and the launch and capture information
are encapsulatedin test data and transferredinto the scan chain.
Theproposedtechniquein[15]focusesonlyonLOSandits im-
plementation on low cost testers. The technique has no impact
on fault coverage and pattern count.
A. Contribution and Paper organization
In this paper, we propose a novel transition fault pattern gen-
eration technique called Enhanced LOC (ELOC). In this tech-
nique,thetransitionlaunchpathis deterministicallydetermined
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D
SD
Q
D
SD
D
SD
QQ
D
SD
Q
(a)
SI1
A
B
SI2
SO2
SO1
1 (block)
0
1
0
1
G1
Y
G3
G4
G2
0
Clk
SEN1
SEN2
(b)
LCIC LC IC IC
SEN2
SC1
SEN1
SENSEN
SENSEN
SC2
Figure 3. Conventional LOC method.
either through a functional path or a em scan path. This im-
provesthecontrollabilityofscanchains, increasesthefaultcov-
erage, reduces the pattern count. A new scan cell, called local
scan enable generator (LSEG), generates the local scan enable
signals (not at-speed), used to control the scan chain mode of
operation. A subset of scan chains are used as functional paths
(like conventional LOC) and the rest are used as scan paths.
This is controlled by scan enable signal; note that dependingon
how the scan enable signal changes during the launch and cap-
ture cycle the scan chain will be controlled either as functional
path or scan path only. In a functionalpath, patternV2 is gener-
ated using the functional response of pattern V1. In scan path,
the patternV2 is generated using the last shift but the responses
are not captured using that scan chain. The scan enable control
informationfor the launchand capture cycle is embeddedin the
test data itself. The LSEG cell has the flexibility to be inserted
anywhere in the scan chain and the hardware area overhead is
negligible.
The rest of the paper is organized as follows. The basic idea
behind enhanced LOC is explained in Section II. Section III
describes the local scan enable generation technique and oper-
ation of the LSEG cell. The scan insertion and the test pattern
generationflowis discussedin SectionIV. SectionV explainsa
case study of a design with fault coverage analysis. The exper-
imental results are presented in Section VI. Finally, concluding
remarks are in Section VII.
II. ENHANCED LAUNCH-OFF-CAPTURE
The LOC method utilizes the functional response of the cir-
cuit to launch the transition at a target gate terminal and prop-
agate the fault effect to an observable point. Launching a tran-
sition through functional response is difficult due to controlla-
bility issues. We now explain the controllability of LOC and
describe how the LOC’s test coverage can be improved by in-
creasing its controllability. Figure 3(a) shows a small example
with two scan chains, SC1 and SC2, each consistingof two scan
cells. The scan-in ports are SI1 and SI2 and the scan-out ports
are SO1 and SO2, respectively. In this particular example, the
two scan chains have independent scan enable signals SEN1
and SEN2, respectively.
D
SD
QD
SD
Q
SEN1
SEN2
(b)
Clk
ICIC CCIC LC
SEN2
SEN1
(a)
SENSEN
SC1
SC2
G1
Y
G2
G3
G4
SI1
A
B
SI2
SO2
SO1
0
0
1
1
1
1
0
1
1
SDSD
SEN
D DSENQQ
Figure 4. Enhanced LOC (ELOC) method.
Consider a slow-to-rise transition fault at the target node Y
(see Figure 3(a)). To launch a 0
site using LOC, the scan cell SC22(suffix indicates the position
from the scan-in port) must contain a logic 0 at the end of the
scan shift operation (V1 applied). The functional response of
the circuit must be logic 1 at the output of gate G1 which is
required to launch a 0
1 transition at Y during the launch
cycle through the functional path as shown. To propagate the
transition, the inputs of gate G4 other than the input Y must
have a non-controllingvalue (0). However, logic 1 at the output
of the gate G1, blocks the propagation of the transition to an
observable point. Therefore, the slow-to-rise transition fault at
thetargetnodeYisuntestablebytheconventionalLOCmethod.
The scan enable signals are high during the shift operation and
low during the launch and capture cycles (see Figure 3(b)).
In some cases, the controllability can be improved by using
the scan path instead of the functional path. Figure 4(a) shows
the same example in which the slow-to-rise transition fault at
node Y, untestable using conventional LOC method, is testable
bycontrollingthe launchpath of the targettransitionfault using
the scan enable signals. The 0
through the scan path instead of the functional path. The re-
maining inputs of the gate G4 other than the target fault site
Y are controllable to non-controlling value 0 to propagate the
transition. The new method is referred to as enhanced launch-
off-capture (ELOC). Figure 4(b) shows the scan enable signals
SEN1 and SEN2 during the shift (IC), launch (LC) and capture
(CC) cycles. In this method, the scan enable signal of the sec-
ond scan chain SEN2 is kept constant at 1 during both launch
and capture cycles. In other words, the scan chain SC2 is used
only to shift bits, i.e, to launch transitions in the circuit. It acts
likea shiftregisteranddoesnotcaptureanyfunctionalresponse
of the circuit.
The conventional LOC method may be viewed as a special
condition of the enhanced LOC (ELOC) method, where the
scan enable signals of all the chains are 0 during the launch and
capture cycles. ELOC provides more controllability of launch-
ing the transition either through the scan path or the functional
path. Note that, the scan enable (SEN) signals do not change
between the launch and capture cycles and any scan enable
?
1 transition at the target fault
?
?
1 transition at Y is launched
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COMBO LOGIC
Figure 5. Controllability of Enhanced LOC.
transition is at shift frequency. Figure 5 shows a circuit with
two scan chains, one acting as a shift register and the other in
the functional mode. The transitions in the first scan chain are
launched through the functional path while the transitions from
the second scan chain are launched from the scan path.
III. LOCAL SCAN ENABLE SIGNAL (LSEN) GENERATION
The enhanced LOC method provides more controllability to
launch a transition but requires independent scan enable sig-
nal for each scan chain. Multiple SEN ports can be used, but
this increases the number of pins. The scan enable control in-
formation for all the scan chains differ only during the launch
and capture cycles of the pattern. Hence, the scan enable sig-
nal from the external tester can be utilized for the scan shift
operation and the scan enable control information for only the
launchandcapturecyclescan begeneratedinternally. Thelocal
scan enable generator cells are inserted within the scan chains.
Therefore, the control information is to be passed as part of the
test data. The scan enable control information will be part of
each test pattern and is stored in the tester’s memory.
The normalscan architecturewith a single scan enable signal
from the external tester is shown in Figure 6(a). There are eight
scan flip-flops in the scan chain and the test pattern shifted is
10100110. The external scan enable signal from the tester is
referredtoas theglobalscanenable(GSEN).Figure6(b)shows
the same circuit in which a local scan enable signal is generated
from the test pattern data for the enhanced LOC method. The
internally generated scan enable signal is termed as local scan
enable (LSEN). The main objective is to de-assert GSEN after
the entire shift operation and then generate the LSEN signal
during the launch and capture cycle from the test data. In this
case, the pattern shifted is modified to 1010[C]0110, where C
is the scan enable control bit which is stored in scan flip-flop A
at the end of the scan operation.
One extra scan flip-flop (A) and an OR-gate are added for
the generation of LSEN signal. The output of A is ORed with
GSEN to generate the LSEN signal (see Figure 6(b)). Note
that GSEN is not an at-speed signal. The GSEN signal asyn-
chronously controls the shift operation. The values of the scan
flip-flops during the various shift cycles are shown under each
flip-flop. GSEN is de-asserted after the nth shift (IC) cycle,
where n=9. n is the length of scan chain after inserting new cell
A. After the GSEN signal is de-asserted at the end of the shift
operation,thescan enablecontrolduringthe launchandcapture
cycles is the control bit C stored in A. At the end of the capture
cycle, the LSEN signal is aysnchronouslyset to 1 by GSEN for
scanning out the response. Figure 6(c) shows the detailed pro-
2
3
4
5
6
7
8
9
1
(a)
1010[C]0110
LSEN
GSEN
A
LSEG
GSEN
SOSI
10100110
(b)
C
0
1
0
1
1
0
0
0
1
1
0
1
1
1
0
C
0
1
1
0
C
0
0
1
1
0
C
0
1
0
C
0
1
0
0
1
1
0
0
1
0
1
1
0
IC LC CC
CLK
LSEN = (GSEN+A)
GSEN
C CC
(c)
Figure 6. (a) Scan chain architecture, (b) Local scan enable (LSEN)generation
and (c) LSEN generation process.
cess of shifting the test pattern into the scan chain and also the
timing waveforms. In general:
LSEN
?
?GSEN
?
A
???
?
1
A
if GSEN=1
if GSEN=0
A. Local Scan Enable Generator (LSEG)
As explained earlier, during the launch and capture cycles of
the pattern, the control bit shifted into scan flop A is used as the
scan enablecontrol. Figure 7 shows the LSEG cell architecture.
It consists of a single flop which is used to load the control
information required for the launch and capture cycles. The
port definition is similar to a scan cell and the output of the flop
is fedbacktothefunctionalinputportoftheflip flop. Itconsists
of a scan-in (SENin) pin which takes GSEN signal as input.
An additionalscan-out(SENout) pin (GSEN
LSEN signal. Therefore, after going to a control state (C) at the
endoftheshiftoperation(GSENis de-asserted),LSENremains
in this state as long as it is asynchronously set to 1 by GSEN.
Table I shows the different modes of operation of LSEG cell.
GSEN
1 represents the normal shift operation of the pattern.
When GSEN
0 and C
1, LSEN
acts in the shift mode to launch the transitions (Shift-Launch
mode). The scan chain acts in the conventional LOC method
when GSEN
0 and C
0 (Functional-Launch mode). Note
that the LSEG cell can be inserted anywhere in the scan chain
and it is not connected to the CUT. Hence, it has no impact on
the functional timing and the CUT fault coverage.
The LSEG cell provides a simple mechanism to generate the
local internal scan enable signals. But, it has a shift depen-
dencyfor the following flop in the shift register mode. IfC
the LSEG flip-flop is constant at 1 for the launch and capture
cycles and the flip-flop following the LSEG cell can generate
?
Q)representsthe
?
???
1 and the scan chain
??
?
1,
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SENout
(LSEN)
SENin
(GSEN)
DQ
SD
0
1
FF
Q
CLK
Figure 7. Local scan enable generator (LSEG) cell.
TABLE I
LSEG OPERATION
GSEN
1
0
0
FF
X
1
0
LSEN
1
1
0
Operation
Shift
Shift-Launch
Functional-Launch
only a 0
of coverage for faults which are in the logic cone and require
a 1 0 transition on the flip-flop following the LSEG cell. In
orderto avoidloss of coveragewithoutsignificant changein the
architecture, the LSEG cell is modified such that the LSEG cell
when loaded with the control bit, the cell will remain in this
state and it is not in the shift path during the launch and capture
cycles forC
1. Figure 8 shows the modified LSEG cell archi-
tecture. It consists of an additional multiplexer and it does not
impact the functional path timing. When GSEN
cell is by-passed and the SD pin is directly connected to Q. In
the Shift-Launch mode, the value from the previous flip-flop of
LSEG cell is shifted into its following flip-flop.
?
1 transition at its output. This may result in loss
?
?
?
0, the LSEG
B. Operation of LSEG cell
Figure 9(a) shows the previous example with the LSEG cell
inserted in the scan chain. The value loaded in the LSEG flip-
flop is represented as C (1010[C]0110) in the test pattern. Fig-
ure 9(b) shows the pattern and the timing waveform for the
conventional LOC method. The SENin(GSEN) signal is asyn-
chronously de-asserted at the end of the shift operation. The
SENout (LSEN) signal is generated by the boolean equation
SENout
QSENin. The GSEN signal is high during
the entire shift operation. At the end of the shift operation, the
?
?FF1
?
?
SENin
(GSEN)
SENout
(LSEN)
DQ
SD
FF
CLK
1
0
0
1
Q
Figure 8. Modifi ed Local scan enable generator (LSEG) cell.
SEN (GSEN)
in
SEN (LSEN)
out
in
SEN (GSEN)
SEN (LSEN)
out
Scan−in pattern i
Scan−out response i−1
Scan−in pattern i+1
Scan−out response i
Scan−in pattern i
Scan−out response i−1
Scan−out response i
Scan−in pattern i+1
(a)
Pattern: 1010[C]0110
ELOC: 1010[C]0110
LOC: 1010[0]0110
CC LC IC
Q (FF1)
CLK
CC LCIC
Q (FF1)
CLK
(c)
(b)
A
LSEG
CCCC
CC
Figure 9. Operation of LSEG cell, (a) Scan chain, (b) Conventional LOC and
(c) Enhanced LOC.
GSEN signal is asynchronously deasserted and the LSEN sig-
nal must be logic 0. Hence, the LSEG cell flip-flop must be
constrained to 0 during atpg. After the capture cycle, the LSEN
signal is asynchronously asserted back by GSEN.
For enhanced LOC, similar to conventional LOC, the GSEN
signal is high duringthe entire shift operation. At the end of the
shift operation, the LSEN signal is determined by the control
bit (C) shifted into the LSEG cell flip-flop during the pattern
shift. Figure 9(c) shows the pattern and the timing waveform
for enhanced LOC. The LSEN signal is constant at logic value
C duringthe launchand capturecycle. It can be noticed that the
LSEN transitions are not at-speed. After the capture cycle, the
LSEN is asserted to 1 asynchronously by GSEN.
IV. DFT INSERTION AND ATPG FLOW
A. Test Architecture
TheLSEG-enabledsolutionexplainedinSectionIIIprovides
a method of generating internal local scan enable signals from
the pattern data and global scan enable signal from the external
ATE. The overheadof generatingthe local scan enable signal is
the addition of an LSEG cell in the scan chain. The area over-
head of an LSEG cell is a few extra gates, which is negligible
in modern designs. The methodology is applicable to designs
with multiple clock domains. In general, there can be multiple
scan chains in a design to reduce the test application time as
this is the case for today’s commercial compression tools. The
test application time is directly proportional to the longest scan
chain length in the design. Figure 10 shows a multiple scan
chain architecture with n scan chains. Each scan chain i, where
1
in, consists of an LSEG cell which generates the local
scan enable signal LSENifor the respective scan chain. The
GSEN signal connects only to the SENinport of LSEG cells.
??
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