Parasitic source/drain resistance reduction in n-channel SOI MuGFETs with 15nm wide fins
ABSTRACT We report on a set of process improvements leading to parasitic S/D resistance reduction in n-channel MuGFETs with 60 nm tall and 15 nm wide fins. We experimentally determine the contributions to the parasitic S/D resistance arising from the specific regions of the S/D geometry. A 50% reduction in the S/D resistance (from 1235 to 600 Ω-μm) is achieved by introducing various scaled processes, including EOT reduction, elevated S/D, undoped fins and removal of halos, reduction in S/D spacer width, and smaller gate lengths. The combination of these process enhancements leads to a 2× increase in IDSAT, measured at constant IOFF (=1nA/μm) and VDD=1.3V.
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ABSTRACT: This paper puts forward an advanced consi-deration on the design of scaled multiple-gate FET (MuGFET); the aspect ratio (R h/w) of the fin height (h) to fin width (w) of MuGFET is considered with the aid of 3-D device simulations. Since any change in the aspect ratio must consider the trade-off between dri-vability and short-channel effects, it is shown that opti-mization of the aspect ratio is essential in designing MuGFET's. It is clearly seen that the triple-gate (TG) FET is superior to the conventional FinFET from the viewpoints of drivability and short-channel effects as was to be expected. It can be concluded that the guide-line of w < L/3, where L is the channel length, is essen-tial to suppress the short-channel effects of TG-FET.
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ABSTRACT: This letter describes the impact of major source/drain (S/D) diffusion and extension layouts on the performance of single-fin and multifin triple-gate (TG) FETs. The fundamental tradeoff between drive current and short-channel effects is clearly demonstrated. Two guidelines are introduced for designing multifin TG-FETs: 1) In order to suppress short-channel effects, the extension region should be shallow. However, the extension should be formed along the gate-electrode edge, otherwise, the large overall S/D resistance would become an obstacle to high drivability. 2) In order to realize high drivability, the cross-sectional area of the major S/D diffusion region, which carriers go through, should be large, to suppress the significant drain-induced barrier-lowering effect, and the region should not touch the buried oxide layer.IEEE Electron Device Letters 07/2006; · 2.79 Impact Factor