Conference Paper

Parasitic source/drain resistance reduction in n-channel SOI MuGFETs with 15nm wide fins

IMEC, Heverlee, Belgium
DOI: 10.1109/SOI.2005.1563597 Conference: SOI Conference, 2005. Proceedings. 2005 IEEE International
Source: IEEE Xplore

ABSTRACT We report on a set of process improvements leading to parasitic S/D resistance reduction in n-channel MuGFETs with 60 nm tall and 15 nm wide fins. We experimentally determine the contributions to the parasitic S/D resistance arising from the specific regions of the S/D geometry. A 50% reduction in the S/D resistance (from 1235 to 600 Ω-μm) is achieved by introducing various scaled processes, including EOT reduction, elevated S/D, undoped fins and removal of halos, reduction in S/D spacer width, and smaller gate lengths. The combination of these process enhancements leads to a 2× increase in IDSAT, measured at constant IOFF (=1nA/μm) and VDD=1.3V.

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