Conference Proceeding

Design of PC-programmable digital hearing-testing device

Dept. of Electr. & Comput. Eng., Univ. of Western Ontario, London, Ont.
Canadian Conference on Electrical and Computer Engineering 06/2005; DOI:10.1109/CCECE.2005.1556919 ISBN: 0-7803-8885-2 In proceeding of: Electrical and Computer Engineering, 2005. Canadian Conference on
Source: IEEE Xplore

ABSTRACT The design of PC programmable digital hearing-testing device is described in this paper targeting the testing of hearing impairedness in a laboratory environment. It is used to measure the response of each ear at different frequencies and at different sound pressure level (SPL). The device input is the serial 12-bit data and 7-bit control signal from USB connection while the output signal is sound waves with frequency range from 20 Hz to 20 KHz. This device is designed and simulated in 0.18 mum CMOS technology. It is composed of digital components except for the active filter. The device is designed as a single chip to fit on a 32 Omega headphones and powered by 1.3 V supply. The device is designed without using any ADC and DAC converters. Improved designs of 12-bit counter, clock generator and control are proposed. PWM generator is designed using digital components only to provide more accuracy and reliability. A second order, Butter-worth active low-pass filter is used as demodulator. The SPL output of the device is PC controllable through the USB connection

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