Conference Paper

Design of PC-programmable digital hearing-testing device

Dept. of Electr. & Comput. Eng., Univ. of Western Ontario, London, Ont.
DOI: 10.1109/CCECE.2005.1556919 Conference: Electrical and Computer Engineering, 2005. Canadian Conference on
Source: IEEE Xplore

ABSTRACT The design of PC programmable digital hearing-testing device is described in this paper targeting the testing of hearing impairedness in a laboratory environment. It is used to measure the response of each ear at different frequencies and at different sound pressure level (SPL). The device input is the serial 12-bit data and 7-bit control signal from USB connection while the output signal is sound waves with frequency range from 20 Hz to 20 KHz. This device is designed and simulated in 0.18 mum CMOS technology. It is composed of digital components except for the active filter. The device is designed as a single chip to fit on a 32 Omega headphones and powered by 1.3 V supply. The device is designed without using any ADC and DAC converters. Improved designs of 12-bit counter, clock generator and control are proposed. PWM generator is designed using digital components only to provide more accuracy and reliability. A second order, Butter-worth active low-pass filter is used as demodulator. The SPL output of the device is PC controllable through the USB connection

  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: Voltage feedback is frequently used in class-D switching audio power amplifiers. This paper discusses the design and implementation of a low-cost filterless class-D, unipolar pulse-width modulation switching audio amplifier having a multi-loop voltage feedback scheme. Classical frequency-compensation techniques are used to design and stabilize the three voltage feedback loops implemented in this application. This design method proves to be a cost-effective solution for designing high-fidelity (hi-fi) audio amplifiers. The cost is reduced because no output filter is used, the required switching frequency is half of the one needed if bipolar PWM was used, and no current sensor is needed for feedback purposes. The output impedance is extremely low due to the reduction of the successive voltage loops, making the amplifier less load dependent. Simulation results show that a total harmonic distortion (THD) of 0.005% can be achieved using this topology, as well as a flat frequency response, free of phase distortion in the audio band. Experimental results show the feasibility of this control scheme, since a THD of 0.05% was achieved with a laboratory prototyped amplifier. A comparison of the performance of this audio amplifier with that of some commercial class-D audio amplifiers, reveals that our design can seriously compete with some of the ICs leading the market at a lower cost.
    IEEE Transactions on Consumer Electronics 03/2004; · 1.16 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: A model is described for predicting the harmonic levels introduced by the use of dead time in class-D, PWM-driven audio power output stages. The model demonstrates that the harmonic levels are a function of load impedance, modulation depth, dead time and switching frequency. In addition, measurements show that, for audio applications, dead time is the dominant cause of power stage nonlinearity
    Electronics Letters 07/1999; · 1.07 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: All analog circuits for a remotely controllable subminiature hearing aid are presented. It is feasible to integrate all circuits together with an I2L decoder on a single bipolar chip. The volume level and the cutoff frequency of a high-pass filter can be controlled. Besides, the device can be remotely switched at microphone and telephone coil, and switched into a standby mode. All circuits presented have been tested with a semicustom realization.
    Analog Integrated Circuits and Signal Processing 02/1993; 3(2):91-103. · 0.40 Impact Factor

Full-text (2 Sources)

Available from
Aug 11, 2014