DESIGN OF PC-PROGRAMMABLE DIGITAL HEARING-TESTING DEVICE
Jasbir N. Patel and Z. Abid
Department of Electrical and Computer Engineering,
University of Western Ontario, London, Ontario, Canada.
Email: firstname.lastname@example.org; email@example.com
The design of PC programmable digital Hearing-Testing
Device is described in this paper targeting the testing of
hearing impaired- ness in a laboratory environment. It is used
to measure the response of each ear at different frequencies
and at different sound pressure level (SPL). The device input is
the serial 12-bit data and 7-bit control signal from USB
connection while the output signal is sound waves with
frequency range from 20 Hz to 20 KHz. This device is designed
and simulated in 0.18 µm CMOS technology. It is composed of
digital components except for the active filter. The device is
designed as a single chip to fit on a 32 Ω headphones and
powered by 1.3V supply. The device is designed without using
any ADC and DAC converters. Improved designs of 12-Bit
counter, clock generator and control are proposed. PWM
generator is designed using digital components only to provide
more accuracy and reliability. A second order, Butter-worth
active low-pass filter is used as demodulator. The SPL output
of the device is PC controllable through the USB connection.
Keywords: Digital circuit; hearing-testing device; mixed signal
circuits; VLSI circuit design.
Previously, hearing related devices have been integrated
using bipolar circuit techniques as described in . Recently,
such devices are being implemented using CMOS technologies
to obtain low-power mixed signal systems-on-a-chip.
Different kinds of such devices are available in the market like
digitally programmable analog processors - or embedded
DSP processors -. Digitally programmable analog
processors are low cost and low power devices whereas the
others have more reliability and lower design time.
Other challenge with hearing testing/aid is the power
supply. 1.1V to 1.5V battery is used for circuit operation. To
overcome the voltage requirement in CMOS technologies or
low power constraints, supply multipliers based on charge
pumps  are used ,. However; these doublers increase
the die area and the number of discrete components.
Therefore, power efficiency is reduced. Some state-of–the-art
implementations  use special CMOS process optimizations
which may increase the final integration cost.
In this paper, we propose a design approach based on
digital design techniques. This CMOS circuit design avoids
the use of voltage multipliers and it is intended for full
integration, on a single chip, in a standard CMOS technology
without any process enhancement. Moreover, all components,
except headphone and coupling and bypass capacitors are
designed on a single mixed-signal IC. All the components
except active low-pass filter are digital. Therefore, the design
provides the needed flexibility and reliability without using
complex DSP algorithms. The detailed designs of USB
controller, 12-Bit data register and 7-Bit control register are not
discussed here. In the following sections, we will first describe
all the blocks briefly. Then we will discuss the implementation
in CMOS 0.18 µm process along with the simulation results.
The complete architecture of the proposed design is shown
in Fig. 1. All the blocks, except the H-Bridge and active low-
pass filter blocks, are designed using digital design techniques.
This is to achieve more flexibility, accuracy and reliability.
Other features offered by our device are:
Full audio-range output (from 20 Hz to 20 KHz)
No ADC or DAC converters is used
Fully digital PWM generator
11 to 107 dB SPL range controlled by digital control block
12-Bit accurate resolution
No complex DSP algorithms is used
The description of each block is presented in the next sections.
Fig. 1: Architecture of Proposed Design
CCECE / CCGEI, Saskatoon, May 2005
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2.1. Clock Generator
Two clock frequencies, 1 GHz and 250 KHz, are generated
using digital design technique. 1GHz clock is used in 12-Bit
high speed counter and 250 KHz clock is used for resetting the
Counter to 0, sampling input data in input registers (12-Bit data
register and 7-Bit control register) and resetting PWM pulse to
logic high level. 1 GHz clock is generated using ring-
oscillator. 250 KHz clock is then generated by dividing the 1-
GHz pulse by 4096 using several stages of edge-triggered D
2.2. 12-Bit High-Speed Counter
This is the most important block to generate PWM pulses
digitally. It is operating at 1 GHz speed. 12-Bit high speed
Counter is implemented using 12-bit high speed up-counter
and 12-bit register to store the data. Conditional-sum based
12-bit adder, known for its short time delay , is used to
implement the high-speed up counter. The structure of the
adder is simplified to perform as up-Counter. One of the two
inputs is permanently grounded and carry-in is permanently
connected to VDD. Then the whole structure is simplified to
reach the desired high speed.
2.3. 12-Bit Digital Comparator and PWM logic
12-Bit digital comparator circuit compares the 12-bit data
of the register with 12-bit up-counter value and reset output to
low if both are equal. PWM logic latches this momentary
pulse to low level until rising edge of the reset signal is
detected. As soon as the PWM output goes low, the clock
signal to the 12-bit high-speed Counter is disabled to reduce
the switching activity and dynamic power consumption. These
clock pulses are recovered again when the PWM output signal
2.4. Class-D Amplifier Output Stage and 7-Bit
Some designs of Class-D amplifier output stage are
described in  to . Output stage of Class-D amplifier is
designed in H-bridge pattern to generate differential output.
The 7-bit control signal is used to control the output sound
pressure level (SPL) from 11 dB to 107 dB.
2.5. Active Low-Pass Filter
Active low-pass filter is used to generate sinusoidal audio
waveforms from PWM pulses. One active low-pass filter is
used in each H-Bridge branch. Second order, non-inverting,
dual feedback configuration of Butterworth filter is used .
Most of the designs,  – , adopted passive low-pass
filter using inductor. On-chip inductor occupies large area (of
the IC chip) and their quality factor is low. Therefore, we used
Fig. 2: Clock divider circuit
active-low pass filter design, based on basic circuit elements:
resistors, capacitors and op-amp. These circuit elements are
easy to integrate on a single chip. Active low-pass filters offer
lower chip area and better performance than their passive
counterpart for audio signals.
3. Implementation and Simulation Results
In this section, we will describe the design implementation
and simulation results of all the building blocks.
3.1. Clock Generator
1 GHz clock pulse is generated using a ring-oscillator (a
chain of odd-number inverters). 1 GHz pulse is divided by
4096 by several stages of D-FF as shown in Fig. 2.
‘CLK’ signal of each stage is connected to Q output of
previous stage. D and Q’ of the same flip-flop are connected
together to invert logic level of Q and Q’ signals on every
rising edge of the input clock. Therefore, the frequency of Q
and Q’ is half of the input clock. A total of 12 D-FF are
required to divide 1 GHz clock by 4096.
The simulation results obtained for the clock generator are
shown below in Fig. 3 and Fig. 4. The actual time periods
measured for 1 GHz and 250 KHz are 1.013 nsec and 4.1499
µsec. Therefore, actual frequency obtained is 0.99 GHz and
Fig. 3: 1GHz Clock Pulses
Fig. 4: 250KHz Clock Pulse
Fig. 5: 12-Bit Adder design for 12-Bit High Speed Counter
3.2. 12-Bit High-Speed Counter
This block consists of a 12-bit adder and a 12-bit register.
The 12-bit register can be designed easily using D-FF. The
Design of the 12-bit adder (to add a bit ‘1’) is shown in Fig. 5.
The basic structure of conditional-sum adder is described in 
and . Both of them used multiplexers as the basic building
block. We designed the 12-bit up counter using 2 NOR, 6
NAND, 6 INV, 7 XOR, 2 simplified XOR (both A and A’ is
available externally instead of inverting in XOR block) and 11
MUX gates. We simplified our 12-bit adder design by
connecting one input to ground and the carry-in to the power
supply (VDD). Our counter operates at 1 GHz frequency with
3.3. 12-Bit Digital Comparator and PWM Logic
The 12-bit digital comparator was designed using XNOR,
NAND and NOR gates. Multiple stages of NAND and NOR
gates are used to avoid high fan-in.
The PWM Logic is designed using modified D-FF. The
Fig. 6: (1) 250KHz Clock, (2) Reset Input to PWM Logic, (3)
Digital Comparator Output and (4) Digitally generated PWM
clock sensitivity is changed to active-low and D input is
connected to VDD. Q’ is used to deliver the output PWM signal.
The simulation waveforms for input and output of PWM
logic are shown in Fig. 6. The PWM pulses goes high when
momentary reset pulse (Fig. 6(2)) is available. The PWM
output goes low when low level pulse (Fig. 6(3)) is detected at
the input. The pulse-width of reset pulse (Fig. 6(2)) and digital
comparator output (Fig. 6(3)) are 2nsec and 1nsec respectively.
Fig. 6(4) shows the PWM pulses generated for 20 KHz audio
3.4. Class-D Amplifier Output Stage and 7-Bit
Different Class-D amplifier output stage designs are
described in  to . Among them, we used multiple
stages of MOS transistors. The 7-Bit control logic is the most
challenging part of the overall design. It was implemented
based on digital design technique. This turned out to be very
challenging for SPL below 20dB, and especially below 10dB.
The output sound pressure level (SPL) is controlled from 11 to
107dB in steps of 1dB or 2dB.
3.5. Active Low-Pass Filter
The 2nd order active low-pass filter is designed with non-
inverting op-amp configuration. Dual feedback loops are used
to implement Butterworth filter as described in . Two op-
amps, designed in CMOS technology, are used. The first op-
amp is used to tune the gain of the active low-pass filter. The
second op-amp implements the 2nd order low-pass filter. Both
op-amps have different output stage. The output stage of the
first op-amp is designed with small size transistors. However;
the output stage of the second op-amp is designed with very
large transistors to reduce the output stage resistance and to
supply sufficient current. The cut-off frequency is set to 100
KHz to get flat response up to 20 KHz audio input. 250 KHz
sampling frequency is used in our design to obtain very low
noise and distortion up to 20 KHz frequency. The values of
resistors and capacitors are calculated by considering above
mentioned specifications. The output audio wave for 20 KHz
frequency is shown in Fig. 7.
Fig. 7: Ideal 20K Sine Wave and 20K Output Wave from Our Download full-text
The design of PC programmable digital Hearing-Testing
Device, for high accuracy and reliability applications, is
presented. The device is designed as a single chip to fit on a
32 Ω headphones and powered by 1.3V supply. The device is
designed without using any ADC and DAC converters. New
designs of 12-Bit counter, clock signals generator and control
circuits are used.
Digital design technique is used to generate clock pulses.
Improved design of the clock divider, using D-FF, is also
presented. The requirement of ADC and DAC is eliminated by
using a 12-bit high-speed Counter. The SPL of the device is
PC controllable (through the USB connection) from 11 to 107
dB in steps of 1dB or 2dB. Simulation results, in the form of
input and output waveforms of main design blocks, are also
presented. This PC controlled device offers portability with
increased flexibility and controllability of the output sound
waves in a hearing impaired-ness testing laboratory.
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