ESD-induced internal core device failure: new failure modes in system-on-chip (SOC) designs
ABSTRACT With MOSFET scaling, increased design complexity, and multiple system power domains, ESD failures occur in internal core areas which are not connected to external package pins. A review of the various internal core device failure mechanisms and design recommendations are presented.
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ABSTRACT: Electrostatic discharge (ESD) accounts for over 30% of chip failure which occurred during chip manufacturing. Inadvertent touching by human body or contact with assembler tray can lead to such ESD failures. The most dominant ESD model is the charged-device model (CDM) wherein energy-destructive failure is incorporated resulting from rapid inflow, or outflow, of high current. Conventional modeling and simulations of the CDM are engineered to describe the behavior of ESD protection circuits, hence have a limitation to account for chip-level charge transfer. This paper presents a new methodology to simulate CDM behavior at chip level. A hierarchical approach associated with a CDM macromodel is developed to model a full-chip structure comprised of several functional subsystems and multiple power supplies. Full-chip CDM simulation provides the analysis of chip-level discharge paths and failure mechanisms, especially focusing on the gate oxide reliability. The proposed method can easily be applied to the CDM failure analysis of any product ICs in the early design stage. As an example, simulation results of a mixed-signal application-specific integrated circuit processed in a 0.25-μm CMOS technology show high correlation with the measurement data.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 02/2003; · 1.09 Impact Factor
Conference Proceeding: Boosted and distributed rail clamp networks for ESD protection in advanced CMOS technologies[show abstract] [hide abstract]
ABSTRACT: A new, area efficient, boosted and distributed active MOSFET rail clamp network for I/O pad ESD protection is presented. In addition, a compact new rail clamp trigger circuit with high resistance to false triggering is introduced.Electrical Overstress/Electrostatic Discharge Symposium, 2003. EOS/ESD '03.; 10/2003
Conference Proceeding: A compact, timed-shutoff, MOSFET-based power clamp for on-chip ESD protection[show abstract] [hide abstract]
ABSTRACT: We present a novel RC-triggered, MOSFET-based power clamp for on-chip ESD protection. The cascaded PFET feedback technique is introduced. As with other feedback techniques, only a very small time constant is required for the RC trigger circuit which results in reduced capacitor area and reduced leakage at power-up. If mistriggering occurs, it is self-corrected with this dynamic feedback technique.Electrical Overstress/Electrostatic Discharge Symposium, 2004. EOS/ESD '04.; 10/2004