ESD-induced internal core device failure: new failure modes in system-on-chip (SOC) designs
ABSTRACT With MOSFET scaling, increased design complexity, and multiple system power domains, ESD failures occur in internal core areas which are not connected to external package pins. A review of the various internal core device failure mechanisms and design recommendations are presented.
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ABSTRACT: Verification of ESD safety on full chip level is a major challenge for IC design. Especially phenomena with their origin in the overall product setup are posing a hurdle on the way to ESD safe products. For stress according to the Charged Device Model (CDM), a stumbling stone for a simulation based analysis is the complex current distribution among a huge number of internal nodes leading to hardly predictable voltage drops inside the circuits. This paper describes an methodology for Human Body Model (HBM) simulations with an improved ESD-failure coverage and a novel methodology to replace capacitive nodes within a resistive network by current sources for CDM simulation. This enables a highly efficient DC simulation clearly marking CDM relevant design weaknesses allowing for application of this software both during product development and for product verification.Advances in Radio Science 01/2008;
Conference Paper: Test Chip design for study of CDM related failures in SoC designs[Show abstract] [Hide abstract]
ABSTRACT: During CDM-ESD testing, SoC (System on a Chip) designs may fail either in the pad ring or in the core circuitry, particularly at the power domain crossings. A specially designed test chip allows one to locate the sites at which ESD-induced damage occurs and also to investigate the efficacy of different CDM protection strategies.Reliability Physics Symposium (IRPS), 2011 IEEE International; 05/2011