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Design of an LC-VCO with One Octave Tuning Range

Andreas Kämpe and Håkan Olsson

Radio Electronics LECS, Department Microelectronics and Information Technology, KTH

Electrum 229, 164 40 Kista

Abstract - This paper presents the design of a wideband,

fully integrated LC-VCO. The architecture is fully

differential and has a tuning range from 1.2 GHz to 2.6

GHz. The phase-noise varies within the tuning range

from -138 dBc/Hz to -128 dBc/Hz at 1 MHz frequency

offset. The VCO is implemented in a 0.18µm CMOS

process using a 1.8 V supply. The circuit, including the

bias, consumes only 3.8 mW at 2.6GHz and 8.5mW at 1.2

GHz.

1 INTRODUCTION

As more and more wireless standards, such as WLAN,

DVB and UMTS. are introduced, an elegant solution

would be a multi-standard transceiver [1]. Therefore

there is a need for extremely wideband circuit blocks for

the RF front-end. The VCO is a key building block in

frequency synthesizers. A challenge is to design a

VCO with a wide tuning range maintaining a low phase-

noise and power consumption. The design is further

complicated by the lack of high quality monolithic

inductors and the small capacitance variation of the

varactors for low control voltage, limitated by the

CMOS technology.

Oscillators without LC-tanks such as ring oscillators

can achieve a very wide tuning range but they suffer

from very high phase noise or high power consumption

[2], [3], [4]. On the contrary a fully integrated LC-VCO

can be made with a low phase-noise and with relatively

low power consumption, but they usually suffer from a

narrow tuning range [5], [6].

In this paper, a fully integrated LC-VCO with a tuning

range over one octave is presented. It also exhibits low

phase-noise and low power consumption. The large

tuning range is achieved by the use of an array of

switched capacitors.

2 LC-VCO

For RF transceivers, the LC-type oscillator is superior

in phase noise due to the band pass filtering of the LC

resonator. Harmonics are attenuated and any sideband

noise is reduced.

The VCO’s output frequency is tuned by on-chip

varactors. These varactors should have low parasitic

capacitance and wide tuning range to cope with

process variations. For an LC-VCO to achieve a tuning

range of one-octave, it would require a capacitance

tuning of two octaves, due to the square dependency

of the frequency to capacitance:

1

min

CL

+

p

1

max

CL

+

p

+

⇒=

CCf

Where fmin and fmax denote the highest and lowest

oscillation frequency, tuned by a varactor with a

capacitance that can be varied from Cmin to Cmax. The

tuning capacitor has to have a Cmax/Cmin ratio even

larger than 4 to compensate for the capacitive

parasitics Cp of the negative resistance and the

inductor. Designing an on chip varactor with this large

Cmax/Cmin ratio in a low voltage CMOS process is not

easy, and would result in a large varactor sensitivity

(VCO gain). This is not recommended, since it would

degrade the phase noise performance of the VCO. Low

frequency noise and interference reaching the varactor

would phase-modulate the VCO and be up-converted

to the carrier frequency increasing the phase noise.

)(2

max

p

C

f

=

(1)

)(2

min

p

C

f

=

(2)

44

min

max

min

max

=

+

p

p

CC

f

(3)

3 THE CAPACITOR ARRAY

Achieving a large Cmax/Cmin ratio while having a small

VCO gain can instead be solved by using an array of

switched capacitors as shown in Fig. 1.

Fig. 1: Switched capacitor array.

The switched capacitors are used as band selectors or

as coarse tuning. For fine tuning, a varactor is used.

The switches consists of NMOS transistors due to

their higher transconductance, but there is a tradeoff

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with the transistor size, between loss and capacitive

load. This translates into either a reduced power

consumption or an increased tuning range.

For small losses, the drain source resistance (RDS(ON))

should be reduced

transconductance. Thus a wide transistor with

minimum gate length and a large overdrive (Vgs-Vt)

should be used. For a small capacitive load, the Cgs and

Cgd have to be minimized, requiring a narrow transistor

with minimum gate length. The capacitor array is

shown in Fig. 2

C

by maximizing the

W

4W

2W

2C

C

4C 4C

2C

B0

B1

B2

4R

2R

R

4R

2R

R

Fig. 2: Capacitor array.

The capacitors on both sides of drain and source are

used for band switching, but they also act as coupling

capacitors isolating the biasing voltage from the

negative resistance. The drain and source are biased

via resistors. When the switch is on, the biasing is set

to 0V and the gate to 1.8 V. This maximizes the

overdrive resulting in a reduced RDS(ON). When the

switch is off the bias is set to 1.8 V and the gate is at

0V. This reduces the voltage dependent Cgs and Cgd

capacitance by 20%. The increased overdrive makes it

possible to use smaller transistors which reduce the

capacitive load without increasing the losses.

The oscillation amplitude is determined by the negative

resistance and the load impedance of the LC tank. At

resonance the LC tank has an impedance

(

P

R

Thus the oscillation amplitude increases with the

oscillation frequency. If the tuning range is large, e.g.

one octave, the oscillation amplitude will vary

significantly between fmax and fmin. This requires an

adjustable negative resistance, and is achieved by

changing the biasing

transconductance of gmn and gmp in the negative

resistance. As the control voltage and thereby the

frequency is increased, the biasing current is

)

S

L

R

2

0

w

=

. (4)

current, affecting the

decreased. This bias control guaranties startup, and

ensures constant oscillation amplitude independent of

the oscillation frequency.

4 VCO ARCHITECTURE

All the blocks in the VCO (inductor, varactor, cap-

array, negative resistance) are fully differential to

reduce the sensitivity to power supply variations and

substrate interference. Fig. 3 shows the block diagram

of the VCO. The negative resistance consists of a

cross-coupled complementary structure of n and p-

channel-transistors.The oscillation frequency f0 is

controlled by the LC-tank. The array of capacitors is

switched in or out in discrete frequency steps, while

the varactor is used for fine tuning.

I2I1 I0

Varactor

Cap-array

Fig. 3: Block diagram.

The cross-coupled complementary structure with n-

MOS and p-MOS transistors was chosen due to its

differential operation, large output swing and low

phase-noise for a given current. An (n&p-core)

operated in the current-limited region [7] can achieve

the same oscillation amplitude but with less current

than an n-core structure. The varactor consists of four

accumulation-mode transistors in an anti-parallel

configuration, shown in fig. 4. This enables differential

tuning. The complete varactor has a Cmax/Cmin ratio of

2.

Cntrl+

Cntrl-

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Fig. 4: MOS varactor

5 THE INDUCTOR

In an on chip LC-oscillator the inductor is the dominant

source of loss, but is compensated by the negative

resistance. The Q of an inductor can be increased by

using a differential coil instead of two single coils. The

coupling factor increases the inductance but with

unaffected series resistance.

A fully differential inductor was designed. It has a

diameter of 340 µm and consists of three turns, see Fig.

5.

Fig. 5: Inductor layout.

The inductor is designed by stacking the three top

metal layers M6, M5 and M4 on top of each other.

They are then all connected in parallel to minimize the

series resistance, thereby reducing the phase noise,

2

0

f

2

2

∆

=

f

QP

KT

FS

sig

SSB

. (5)

The disadvantage of this triple layer inductor is the

reduced tuning-range. The metal layers M5, M4 and

lower are closer to the substrate which increases the

capacitive load.

The inductor was designed using Electromagnetic

(EM) simulators such as ASITIC [8] and ADS. The

geometry and size was optimized using ASITIC, then

fine tuned and simulated with ADS. Simulations

(shown in Fig. 6.) resulted in an inductance around 3.6

nH Between 1.0 and 3.0 GHz. The Q varies from 10.5 to

14.5.

1.21.41.6 1.82.02.2 2.4 2.6 2.81.03.0

10

11

12

13

14

9

15

3.65E-9

3.70E-9

3.75E-9

3.60E-9

3.80E-9

Frequency (GHz)

Q

inductance (H)

Q

Inductance

Fig. 6: Inductor performance.

The simulated S-parameter data was fitted to a lumped

model of a transmission line, shown in Fig 7.

MUTIND

Fig. 7: Inductor model.

The extraction of the simulated data to this model

resulted in less than 2% error from 1.2 GHz to 3GHz.

6 RESULTS

The VCO was implemented in a 0.18µm CMOS process

and verified in simulations using Cadence SpectreRF.

This Resulted in a tuning range from 1.2 GHz to 2.6

GHz, shown in Fig. 8.

000 001010 011

Frequency of oscillation

Differential control voltage (V)

Fig. 8: tuning range.

-2.0 -1.00.0

1.0 2.0

2.5

2.4

2.3

2.2

2.1

2.0

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

2.6

2.7

(GHz)

100 101 110111

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The phase-noise at 1 MHz frequency offset varies from

-138 dBc/Hz at 1.2 GHz, to -128 dBc/Hz at 2.6 GHz, The

circuit including the bias, consumes only 3.8 mW at 2.6

GHz versus 8.5mW at 1.2 GHz. The current

consumption of the VCO at 2.6 GHz is 2.1 mA with a

core current of 1.4 mA. The biasing circuitry adds 0.7

mA.

To compare the performance of various VCO’s, a

common approach is to use a figure of merit (FOM),

∆

+=

mWP

f

f

0

S FOM

VCO SSB

/

2

(2)

FOM normalizes the phase noise to offset frequency,

oscillation frequency and power consumption PVCO.

This results in a FOM of -190 dBc/Hz for this design. In

The table below, some VCOs from litterature are listed.

Our design has an overall very good performance

expressed in FOM and superior if the wide tuning

range is taken in account.

VCO Tech

[µm]

[4] 0.25

[6] 0.25

[9] 0.25

[10] 0.18

[11] 0.13 SOI

This 0.18

* Quadrature VCO

Tuning range

[%]

18

28

17

16

58.7

74

FOM

[dBc/Hz]

-183

-183

-185.5*

-174.5*

-186.6

-190

6 CONCLUSIONS

In this paper we have presented a low power, low-

phase noise VCO having a tuning-range over one

octave (1.2 to 2.6 GHz). The VCO is completely

differential (even the tuning is differential). The VCO is

implemented in a 0.18µm CMOS process using a 1.8 V

supply. Simulation at 2.6 GHz oscillation frequency,

showed a phase noise of -128 dBc/Hz at 1 MHz

frequency offset. The VCO, including the bias,

consumes only 3.8 mW.

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