Conference Proceeding

Poly-Si/high-k gate stacks with near-ideal threshold voltage and mobility

IBM Semicond. R&D Center, Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
05/2005; DOI:10.1109/VTSA.2005.1497093 ISBN: 0-7803-9058-X In proceeding of: VLSI Technology, 2005. (VLSI-TSA-Tech). 2005 IEEE VLSI-TSA International Symposium on
Source: IEEE Xplore

ABSTRACT We demonstrate poly-Si/high-k gate stacks suitable for successful implementation in low power technologies. An optimized gate dielectric process was employed to suppress the large pFET threshold voltage shift commonly found with Hf-based gate dielectrics, reducing it to -0.2 V, while preserving pFET and nFET device performance.

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Keywords

large pFET threshold voltage shift
 
nFET device performance
 
pFET
 
successful implementation
 

M.M. Frank