A Hardware Architecture for Elliptic Curve Cryptography and Lossless Data Compression

Abstract

We present a hardware architecture that combines Elliptic Curve Cryptography (ECC) and lossless data compression in a single chip. Input data is compressed using a dictionary-based lossless data compressor before encryption, then; two elliptic curve cryptographic algorithms can be applied to the compressed data: ECIES for encryption or ECDSA for digital signature. Applying data compression presents three advantages: first, the improvement in the cryptographic module throughput by reducing the amount of data to be encrypted; second, the higher utilization of the available bandwidth if encrypted data is transmitted across a public network and third, the increment of the difficulty to recover the original information. The architecture was described in VHDL and synthesized for a Xilinx FPGA device. The results achieved show that it is possible to combine these two algorithms in a single chip while gathering the advantages of compression and cryptography. This work is novel in the sense that no such algorithm combination has been reported neither a hardware implementation of elliptic curve cryptographic schemes.

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Hardware architecture for elliptic
curve cryptography and lossless
data compression
by
Miguel Morales-Sandoval
A thesis
presented to the National Institute for Astrophisics, Optics and Electronics
in partial fulfilment of the
requirement for the degree of
Master of Computer Science
Thesis Advisor:
Dra. Claudia Feregrino-Uribe
Computer Science Department
National Institute for Astrophisics, Optics and Electronics
Tonantzintla, Puebla
M´ exico
December 2004

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Abstract
Data compression and cryptography play an important role when transmitting data
across a public computer network. While compression reduces the amount of data to
be transferred or stored, cryptography ensures that data is transmitted with reliability
and integrity. Compression and encryption have to be applied in the correct way: data
are compressed before they are encrypted. If it were the opposite case the result of the
cryptographic operation would be illegible data and no patterns or redundancy would
be present, leading to very poor or no compression. In this research work, a hardware
architecture that joins lossless compression and public-key cryptography for secure data
transmission applications is discussed. The architecture consists of a dictionary-based
lossless data compressor to compress the incoming data, and an elliptic curve crypto-
graphic module that performs two EC (elliptic curve) cryptographic schemes: encryp-
tion and digital signature. For lossless data compression, the dictionary-based LZ77
algorithm is implemented using a systolic array aproach. The elliptic curve cryptosys-
tem is defined over the binary field F2m, using polynomial basis, affine coordinates and
the binary method to compute an scalar multiplication. While the model of the complete
system was implemented in software, the hardware architecture was described in the
Very High Speed Integrated Circuit Hardware Description Language (VHDL). A pro-
totype of the architecture was implemented on a Xilinx Virtex II Field Programmable
Gate Array (FPGA) device. Two advantages of combining lossless compression and
public-key encryption were demonstrated: 1) the improvement in the cryptographic
module by reducing the amount of data to be encrypted, and 2) a better utilization of
the available bandwidth when encrypted data is transmitted across a public computer
network.
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Resumen
Cryptograf´ ıa y compresi´ on de datos son dos tecnologias centrales en aplicaciones de
red. La compresi´ on reduce la cantidad de datos permitiendo ahorro de espacio de
almacenamiento o reducci´ on de tiempo para realizar la tranferencia de los datos. Por
otra parte, la criptograf´ ıa garantiza que los datos se transmitan con confiabilidad e
integridad. Cuando ambos algoritmos se combinan, la compresi´ on debe ralizarse primero
y a continuaci´ on el cifrado. Si la aplicaci´ on de los algoritmos se realizara en el orden
inverso, el resultado de la operaci´ on de cifrado dar´ ıa como resultado datos totalmente
inenteligibles con muy poca o nula redundancia. Cuando la compresi´ on fuera aplicada,
el resultado ser´ ıa pobre o nula.
En este trabajo de investigaci´ on se presenta una arquitectura hardware que combina
compresi´ on de datos sin p´ erdida y criptograf´ ıa de llave p´ ublica para aplicaciones de
transmisi´ on segura de datos. La arquitectura consiste de un compresor de datos sin
p´ erdida basado en diccionario y un m´ odulo que ejecuta dos esquemas de criptograf´ ıa de
curvas el´ ıpticas (ECC): cifrado y firma digital. El m´ etodo de compresi´ on seleccionado es
el LZ77 implementado bajo el enfoque de arreglos sist´ olicos. El criptosistema de curvas
el´ ıpticas se define sobre el campo binario F2m usando base polinomial y coordenadas
affine. El m´ etodo binario es utilizado para realizar la operaci´ on de multiplicaci´ on escalar.
Una implementaci´ on en software del sistema propuesto fue realizada a fin de validar
la arquitectura hardware. El sistema completo fue descrito usando el lenguaje est´ andar
para descripci´ on de hardare VHDL, fue simulado en Active-VHDL y sintetizado para la
familia de FPGAS (Field Programmable Gate Array) Virtex II de Xilinx. Las ventajas
que presenta el enfoque de combinar compresi´ on de datos com criptograf´ ıa son: 1) el
mejoramiento en el desempe˜ no del modulo criptogr´ afico al reducir la cantidad de datos
a ser procesados y, 2) una mejor utilizaci´ on del ancho de banda disponible cuando la
informaci´ on se transmite a trav´ es de una red.
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