A sub-100 μW 1.9-GHz CMOS oscillator using FBAR resonator
ABSTRACT The paper presents an ultra-low power CMOS oscillator using film bulk acoustic resonator (FBAR). The 1.9-GHz oscillator consumes 89 μW from a low supply voltage of 430 mV and achieves an excellent phase-noise performance of -98 dBc/Hz, -120 dBc/Hz and -138 dBc/Hz at 10 kHz, 100 kHz and 1 MHz offset, respectively. The oscillator is implemented in a standard 130 nm CMOS process and packaged using chip-on-board techniques. Compared with other state-of-the-art oscillators, this oscillator has the best figure-of-merit (Ham, D. et al., IEEE J. Solid State Circuits, vol.36, no.6, p.896-909, 2001). To the authors' knowledge, this is the first sub-100 μW GHz-range oscillator reported.
Conference Proceeding: A 1900MHz-band GSM-based clock-harvesting receiver with −87dBm sensitivity[show abstract] [hide abstract]
ABSTRACT: A 0.13μm CMOS clock-harvesting receiver is presented which extracts a 21Hz clock embedded within the GSM standard for the wake-up of a wireless sensor network. In active mode, the receiver achieves -87dBm sensitivity with 57μs of jitter at the output while consuming 126μW. The receiver is optimized for heavy duty-cycling with a sleep-mode power consumption of only 81pW.Radio Frequency Integrated Circuits Symposium (RFIC), 2011 IEEE; 07/2011
A Sub- 1 OOpW 1.9-GHz CMOS Oscillator Using FBAR Resonator
Y. H. Chee, A. M. Niknejad, J. Rabaey
Berkeley Wireless Research Center, Dept. of EECS, UC Berkeley, Berkeley, CA 94704, USA
Abstract - This paper presents an ultra-low power
CMOS oscillator using Film Bulk Acoustic Resonator
(FBAR). The 1.9-CHz osciIIator consumes 89pW from a low
supply voltage of 430mV and achieves an excellent phase-
noise performance of -98 dBc/Hz, -120 dBclHz and -138
dBc/Hz at IOlcHz, 1OOkHz and lMHz offset respectively. The
oscillator is implemented in a standard 130nm CMOS
process and packaged using chip-on-board techniques.
Compared with other state-of-the-art oscillators, ’ this
oscillator has the best figure-of-merit 1 1 1 . To the authors’
knowledge, this is the first sub-100pW GHz-range oscillator
Index Terms - FBAR, MEMS, low power, oscillators,
Gigahertz range oscillators are essential building blocks
in today’s communication, computing and networking
systems. These applications require a small form factor,
low cost, low power and low phase noise oscillator. For
example, in wireless sensor networks, the average power
of the sensor node needs to be 100’s of pW to enable
energy scavenging while its size has to be < lcm3 [Z].
On-chip CMOS LC oscillators are fully integrated but
consume more power and have mediocre phase-noise
performance . Alternatively. using high Q off-chip
SAW and transmission
resonators) leads to lower power dissipation and better
phase noise performance but are more bulky 14-61.
Unlike other resonators, FBAR 173 offers both small
size and high Q simultaneously. Coupled with good circuit
design, this leads to a compact, low power and IOW phase
noise oscillator. In addition, they can be integrated with
active devices to form a fully integrated, low cost solution
This paper describes the design and implementation of a
1.9 GHz ultra low power FBAR oscillator with good
phase noise performance.
follows: section II presents the characteristics of the
FBAR, section 111 explains the techniques used in low
power oscillator design, section IV jllustrates its
implementation, section V discusses the experimental
results and section VI concludes this paper.
The paper is organized as
1 1 . FBAR RESONATOR
The FBAR  consists of a thin layer of piezoelectric
electrodes, which are supported by a micro-machined
substrate as shown in Fig. 1. The metaliair interfaces serve
as excellent reflectors to form a high Q acoustic resonator.
The unloaded Q of the FBAR resonator is >lo00 and it
occupies about 1 OOpm x 1 OOpm.
between two metal
Fig. 1 Cross-section of the FBAR resonator
The FBAR resonator can be modeled using the
Modified Buttenvorth Van Dyke circuit as shown in Fig. 2
and R, are its motional inductance,
capacitance and resistance respectively. L, and CO models
the parasitic series inductance and parallel plate
capacitance due to the two metal electrodes respectively.
Electrode and material losses are accounted by R, and &
Fig. 2: Circuit model for the FBAR resonator
Fig. 3 shows the frequency response of the FBAR
resonator. The FBAR resonator is capacitive at most
f?equencies except for a narrow band of frequencies
between its series and parallel resonance, where it is
inductive. In these range of frequencies, the FBAR
resonator behaves like a high Q inductor which can be
used to build a low power, low phase noise oscillator.
2005 IEEE Radio Frequency Integrated Circuits Symposium
Fig. 3: Frequency response of the FBAR resonator
1 1 1 LOW POWER OSCILLATOR DESiGN
The schematic of the oscillator is shown in Fig. 4. The
oscillator uses the Pierce configuration with a CMOS
inverting amplifier composed of transistor M1 and M2. A
large resistor Rb is used to bias the gate and drain voltage
of transistors M1 and M2 at Vdd2 to maximize the
allowable voltage swing and minimize its loading on the
Fig. 4: Schematic of the FBAR oscillator
Transistors MI and M2 share the same current but their
transconductances sum. Thus, only about half the current
is needed to provide the necessary transconductance for
oscillation. To reduce the power further, the transistors
MI and M2 are designed to operate in the sub-threshold
regime to maximize their current efficiency (gm/Id). In
addition, the drain-source voltage of transistors M 1 and
M2 is designed to be at least a few kT/q to achieve a high
output resistance and minimize its loading on the
Capacitors C , and C2 transform the transconductance of
the inverting amplifier into a frequency dependent
negative resistance, -R.
The impedance looking from
FBAR (across node X and node U) is the given as
where o is the angular frequency and Gml, Gm2 are the
large.signa1 transconductances of transistor M 1 and M2.
At the frequency of oscillation (Q,~~, the FBAR behaves
like an inductor Le, in series with resistance ks.
sustain steady state oscillation, %q = R, or
From eqn. (2), small values of C, and C2 are desirable
as they require less G, to sustain steady state oscillation,
resulting in lower power consumption. Thus, for this
design, capacitors C, and C2 are solely composed of the
transistors’ gate and drain capacitances, interconnect
capacitances and pad capacitances and no explicit
capacitance is added. Also, C, is set to be equal to C2 to
yield the best negative resistance at the frequency of
IV . IMPLEMENTATION
The oscillator is implemented in a standard 0.13ym
CMOS process from ST Microelectronics. The FBAR
resonator and the CMOS die are packaged together onto a
test board using chip-on-board techniques as shown in
Fig. 5. Two short bond wires are used to connect the
FBAR to the CMOS die to minimize parasitic and avoid
any spurious oscillations. Each bond wire is estimated to
be -250pH and is taken into account in the design. The
oscillator is connected to an on-chip buffer to provide a
50R output. The entire oscillator is about 1.7”
O.Xmm. The oscillator core occupies only 40pm x 40pm.
For more compact implementation, the FBAR die can be
flip-chip on top of the CMOS die, or the resonator can be
integrated with the active devices .
Fig. 5: Die Photo of the FBAR oscillator
As shown in Fig. 5, the bond pads for the FBAR's
electrodes are not identical. The smaller force electrode
has a pad capacitance of 2OfF whereas the larger sense
electrode has a pad capacitance of 150s. On the other
hand, the totaI gate Capacitance of MI and M2 is about
330fF and their total drain capacitance is about 200fF.
Thus, connecting the gate node to force electrode and the
drain node to the sense electrode results in C, = Cz, which
maximizes the negative resistance at the oscillation
fiequend y .
V. EXPERIMENTAL RESULTS
The oscillator is self-biased with a 430mV supply and
dissipates 89pW for sustained oscillations at 1.882 GHz.
The measured zero to peak output swing of the oscillator
is 142mV. The output spectrum of the oscillator is shown
in Fig. 6. A clean output signal is obtained and no close-
in spurs are observed, indicating the absence of low
frequency parasitic mechanical resonances. Second, third
and fourth and fifth harmonics are measured to be -43.8
dBc, -45.5 dBc, -68.8 dBc and -69.7 dBc respectively.
The phase noise performance is shown in Fig. 7. The
measured phase noise at IOkHz, lOOkHz and lMHz offset
is -98 dBc/Hz, -120 dBciHz and -138 dBc/Hz
Good phase noise performance is mainly
attributed to the high Q factor of the resonator.
A better phase noise performance can be obtained by
operating the oscillator at the edge of the current limited
regime with higher power consumption [I]. Fig. 8 shows
the zero-to-peak output voltage swing and measured phase
noise for various power consumptions. The best phase
noise performance occurs when the output voltage swing
is 167mV and oscillator dissipates 104pW. The optimal
phase noise is -100 dBcMz, -122 dBc/Hz and -140
dBc/Hz at IOkHz, 1 OOkHz'and lMHz offset respectively.
Beyond this operating point, the oscillator transits into the
voltage limited regime where the output resistance of the
transistors decreases and loads the oscillator, resulting in
poorer phase noise performance.
Fig, 6: Output frequency spectrum
1 Ok 1 OOk
Frequency offset (Hz)
Fig. 7: Measured phase noise performance
a , E 150
Power Consumption (wW)
Fig. 8: Measured output voltage swing and phase noise
performance for various power consumptions.
Phase Noise Process
Resonator / Inductor
I FOM I
Table 1 : Comparison with state-of-the-art oscillators
To evaluate the performance of this oscillator, a unit-
less power-frequency-normalized figure of merit (FOM) is
used [l]. The FOM is defined as:
where PDc is the‘ DC power consumption of the oscillator,
is the phase noise of the oscillator at an offset
frequency foFFsET from its oscillation fiequencyf&,
the Boltzmann constant and T is the temperature in
Kelvin. Table 1 shows that our oscillator has the best
FOM compared to other state-of-the-art GHz-range
oscillators, In this design, we have used 0.18pm channel
length and hence the 6.6dB improvement over previous
design [lo] is mainly due to low power circuit design
techniques discussed in section 111.
We have presented an ultra-low power 1.9-GHz CMOS
oscillator using FBAR resonator, The oscillator draws
89pW from a 430inV supply and achieves a phase-noise
of -98 dBciHz, -120 dBc/Hz and -138 dBc/Hz at IOkHz,
IOOkHz and lMHz offset respectively. Compared with
other state-of-the-art oscillators, our oscillator has the best
FOM. To the authors’ knowledge, this is the first sub-
1 OOpW GHz-range oscillator reported.
This low power oscillator can be employed in a direct
modulation transmitter (e.g. for low data rate wireless
sensor network applications) where the digital data is
modulated on to the RF carrier by on-off cycling the
oscillator. Alternatively, a digitally controlled capacitive
bank or a varactor can be added for fiequency tuning,
converting it into a VCO.
The authors would like to thank M. Frank and B. Otis
for their support in this work, We also like to thank
Agilent Technologues and ST Microelectronics for the
FBAR resonator and CMOS fabrication respectively. This
research was fimded in part by DARPA (Grant No.
N6600 1 -0 1-1 -8967).
D. Ham, et al., “Concepts and methods in optimization of
integrated VCOs”, IEEE Joumal of Solid Stare Circuits,
vol. 36, no. 6, pp. 896-909, Jun 2001.
J. Rabaey, et al., “PicoRadios for Wireless Sensor
Networks: The Next Challenge in Ultra-Low Power
Design”, Digest of Technical Papers, International Solid
Stare Circuits Conference (ISSCC) 2002, pp. 200-20 I, Feb
T. Song, et al., “A SGHz transformer coupled CMOS VCO
using bias-level shifting technique”, Digest of IEEE 2004
Radio Frequency Integrated Circuits (RFIC} Symposium,
pp. 127-130, Jun 2004.
. I , Steinkamp, et al. ,“A 5.84 GHz tunable SAW oscillator
with frequency doubler for a DSRC system”, Digest of
IEEE 2003 Radio Frequency Integrated Circuits (RFIC)
Symposium, pp. 483-486, Jun 2003.
D. Linten, et al., “A 328pW 5GHz voltage-controlled
oscillator in 90nm CMOS with high-quality thin-film post-
processed inductor“, Proceedings o f IEEE 2004 Custom
Integrated Circuits Conference (CKC), pp. 70 1-704, Oct
S. H. Cheng, et at., ” Low phase noise integrated voltage
controlled oscillator design using LTCC technology”, IEEE
Microwave and Wireless Components Letters, vo1.13, no. 8,
pp. 329-33 1, Aug 2003.
R.C. Ruby, et al., “Thin film bulk wave acoustic resonators
(FBAR) for wireless applications”, Proceedings of IEEE
2001 Ultrasonics Symposium, vol. 1, pp. 813-821, Oct
M. Dubois, et al., “Integration of High-Q BAW resonators
and filters above IC”, Digesr of Technical Papers,
Infernational Solid State Circuits Conference (ISSCC)
2005, pp. 392-393, Feb 2005.
J. D. Larson 111, et al., “Modified Butterworth-Van Dyke
circuit for FBAR resonators and automated measurement
systems”, Proceedings of IEEE 2000
Symposium, vol. 1, pp. 863-868, Oct 2000.
[lo] B. P. Otis, et al., “A 300-pW 1.9-GHz CMOS oscillator
utilizing micromachined resonators”, IEEE Journal o f Solid
State Circuits, vol. 38, no. 7, pp. 1271-1274, JulZOO3.