A CMOS 2.45-GHz radio frequency identification tag IC with read/write memory
ABSTRACT A 2.45-GHz RFID tag chip was designed on standard 0.25- μm CMOS process. Using only MOS devices, the low-Vt rectifier circuit produces 100 μW of power with 2 dBm input. The tag IC with bidirectional communication and anti-collision features can be read from a distance of up to 15 cm under a reader power of 250 mW. The die area of 0.79 mm2 includes a 128-bit rewritable non-volatile memory.
Conference Proceeding: AC-only RF ID tags for barcode replacement[show abstract] [hide abstract]
ABSTRACT: An RF ID concept using ac-powered circuits without DC conversion is demonstrated for barcode replacement. A 32b codeword ID tag including an RF front-end, voltage limiter, frequency divider, ROM and power modulator has a 0.02mm<sup>2</sup> area in a 0.13μm CMOS process. A packaging technology uses a sidewall contact to facilitate the assembly process.Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International; 03/2004
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ABSTRACT: A novel organization of switched capacitor charge pump circuits based on voltage doubler structures is presented in this paper. Each voltage doubler takes a dc input and outputs a doubled dc voltage. By cascading n voltage doublers the output voltage increases up to 2<sup>n </sup> times. A two-phase voltage doubler and a multiphase voltage doubler (MPVD) structures are discussed and design considerations are presented. A simulator working in the Q-V realm was used for simplified circuit level simulation. In order to evaluate the power delivered by a charge pump, a resistive load is attached to the output of the charge pump and an equivalent capacitance is evaluated. A comparison of the voltage doubler circuits with Dickson charge pump and Makowski's voltage multiplier is presented in terms of the area requirements, the voltage gain, and the power level. This paper also identifies optimum loading conditions for different configurations of the charge pumps. Design guidelines for the desired voltage and power levels are discussed. A two-stage MPVD was fabricated using MOSIS 2.0-μm CMOS technology. It was designed with internal frequency regulation to reduce power consumption under no load conditionIEEE Transactions on Circuits and Systems I Fundamental Theory and Applications 04/2001;
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ABSTRACT: This paper presents a novel fully integrated passive transponder IC with 4.5- or 9.25-m reading distance at 500-mW ERP or 4-W EIRP base-station transmit power, respectively, operating in the 868/915-MHz ISM band with an antenna gain less than -0.5 dB. Apart from the printed antenna, there are no external components. The IC is implemented in a 0.5-μm digital two-poly two-metal digital CMOS technology with EEPROM and Schottky diodes. The IC's power supply is taken from the energy of the received RF electromagnetic field with help of a Schottky diode voltage multiplier. The IC includes dc power supply generation, phase shift keying backscatter modulator, pulse width modulation demodulator, EEPROM, and logic circuitry including some finite state machines handling the protocol used for wireless write and read access to the IC's EEPROM and for the anticollision procedure. The IC outperforms other reported radio-frequency identification ICs by a factor of three in terms of required receive power level for a given base-station transmit power and tag antenna gain.IEEE Journal of Solid-State Circuits 11/2003; · 3.06 Impact Factor