Constant–gmrail–to–rail input/output Op–Amp for video applications

Abstract

An operational amplifier (op-amp) with input output (I/O) rail-to-rail (r-t-r) capability suitable for video applications is presented. The input stage provides a constant transconductance value over the entire input common-mode range, whereas a class-AB output stage with an accurate control of the quiescent current ensures r-t-r output swing. Both the input stage transconductance and the output stage quiescent current are controlled by means of static loops, which allows high-frequency operation of the amplifier. Experimental results from a 0.8-µm CMOS test chip are shown.

Full text

Page 1

Constant-gm Rail-to-Rail Input/Output Op-Amp for Video Applications
Juan M. Carrillo(1), José L. Ausín(1), J. Francisco Duque-Carrillo(1), and Guido Torelli(2)
(1)Dept. of Electronics and Elec. Eng.
University of Extremadura
06071 Badajoz, Spain
jmcarcal@unex.es
(2)Department of Electronics
University of Pavia
27100 Pavia, Italy
guido@ele.unipv.it
Abstract
An operational amplifier (op-amp) with input/output
(I/O) rail-to-rail (r-t-r) capability suitable for video appli-
cations is presented. The input stage provides a constant
transconductance value over the entire input common-
mode range, whereas a class-AB output stage with an
accurate control of the quiescent current ensures r-t-r
output swing. Both the input stage transconductance and
the output stage quiescent current are controlled by means
of static loops, which allows high-frequency operation of
the amplifier. Experimental results from a 0.8-µm CMOS
test chip are shown.
1. Introduction
At present, rail-to-rail (r-t-r) operation of analog cir-
cuits has become mandatory in order to obtain an acceptable
signal-to-noise ratio in low-voltage environments. The de-
sign of an r-t-r output stage able to sweep from one sup-
ply to the other is not a great obstacle. Nevertheless, the
main limitation lies at the input. Typical operational am-
plifier (op-amp) input stages based on a simple differen-
tial pair present a very limited input common-mode
(CM) voltage range in the positive or the negative supply
direction. Thus, complementary differential input stages
have to be used, as shown in Fig. 1(a) (ignoring the float-
ing voltage sources VS for the moment). This leads to the
need for controlling the total transconductance (gm,tot) of
the input stage (which is the sum of the transconduc-
tances of the n-channel, gm,n, and p-channel, gm,p, differ-
ential pairs) in order to avoid its large variation [Fig.
1(b)], which arises as the operating point of the two input
pairs depends on the input CM level [1-6].
2. Constant-gm rail-to-rail input stage
Different circuit techniques for maintaining the trans-
conductance (gm) of r-t-r op-amps constant over the
whole input CM range have been proposed [1-6]. Many
of these techniques are based on dynamic feedback
loops, that limit the speed performance of the amplifier
[1-3, 5]. One of the simplest techniques to improve the op-
amp performance in this respect consists in shifting the
CM response of the PMOS (NMOS) input differential
pair in the negative (positive) direction so as to make its
transition region (i.e., the input CM voltage range where
its tail current source operates in the triode region) to
IBp
IBp
IBn
VSS
VSS
VDD
VDD
VS
VS
VS
VS
++
−−
++
−−
Vi+
Vi+
Vi+
Vi
Vi
Vi
−−−
M1PM1P
M2PM2P
M1NM1N
M2N M2N
MBPMBP
MBN MBN
IBn

(a)
VDD
0
VSS
0
50%
100%
gm
gm,n
gm,p
gm,tot
Vi,cm
(b)

VC
0
50%
100%
0
VDD
VSS
gm
gm,n
gm,p
gm,tot
Vi,cm
(c)

Fig. 1. (a) Typical rail-to-rail CMOS amplifier input stage (ignoring
the floating voltage sources VS). Transconductance variations
(b) with VS = 0 and (c) with CM response overlapping (VS > 0).

overlap that of the complementary pair, according to a
predetermined design criterion. In practice, overlapping
the transition regions in an r-t-r input stage can be
achieved by adding an appropriate constant voltage VS to
the input CM component applied to the PMOS (NMOS)
differential pair, as shown in Fig. 1(a), so as to obtain the
gm performance illustrated in Fig. 1(c). The idea of CM
response overlapping has been recently introduced [6].
However, no tuning section for adjusting the optimal VS
value has been proposed which, in practice, strongly lim-
its the applicability of the reported technique.
A sound criterion for tuning the transition region
overlapping consists in choosing the value of VS so that
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VSS
VSS
I(VC)I(VC)
Vo1= VC
Vo1= VC
A1A1A1
CC
CC
VDD
VDD
MA MA
M1AM1A
M1BM1B
IB
IB
MBMB
M2AM2A
M2B M2B
A2 A2 A2
A5 A5A5
A3A3A3
A4 A4A4
Tn1
Tn1
Current summing
and gain stageand gain stage
(a)
Tn2
Tn2
in1
in1
in1
+++
in1
in1
−−
in2
in2
in2
+++
in2
in2
−−
Current summing
−in1
−in2

VSS
VSS
IBp(VC+VS)
M4A
M4BM4B
IBp
IBp
VDD
Vo2
Vo2
A1A1A1
M3AM3A
M3BM3B
A2 A2A2
A3A3A3
A4A4 A4
Tp1
Tp1
Current
summing summing
MCMC
MDMD
Vo2
Vo2
MSA MSAMSCMSC
MSBMSB
MSD
VS
+
VS
+
VS
VS
++
Tp2
Tp2
−−
−−
IBp(VC+VS)
M4A
VDD
Current
MSD

(b)
Current
summingsumming
(c)
VSS
VSS
A1 A1A1
VDD
Vo3
Vo3
MEME
M5A M5A
M5BM5B
IB
IB
A2A2A2
IBp
IBp
MFMF
M6AM6A
M6BM6B
A1A1A1
A2A2A2
Tn
Tn
Tp
Tp
Current
VDD

IR
IR
R 2R 2R 2
R 2R 2R 2
RR
RR
A1A1A1
−V 2
−V 2
−V 2
V 2
V 2
V 2
Vo1= VC
Vo1= VC
VC−V
VC−V
VC+V
VC+V
A3A3A3
A4A4A4
A2A2 A2
A5A5A5
++
VDD
VDD
VSS
VSS
IR
IR
IR
IR
IR
IR

(d)
Fig. 2. Circuit implementation of the tuning section for (a) VC, (b) VS
and (c) IBp; (d) generator of the dc differential voltages
for the schemes in Figs. 2(a), 2(b), and 2(c).

the cross point of the transition regions takes place where
gm,n and gm,p are halved with respect to their maximum
values over the entire Vi,cm range (i.e., to their values at
the extreme positive and negative input CM voltages,
respectively). An automatic tuning for achieving a CM
response overlapping according to the above constant-gm
criterion, can be realized in two steps, each carried out
by a separate circuit section. The first section must pro-
vide the input CM level [VC in Fig. 1(c)] for which the
transconductance of the input pair without floating volt-
age sources [i.e., of the NMOS pair in Fig. 1(a)] is
halved with respect to its maximum value. The second
tuning section must provide the VS shifting value for
which, when Vi,cm = VC, the transconductance of the
complementary pair [i.e., of the PMOS pair] is also
halved with respect to its maximum value.
Fig. 2(a) shows the circuit block suitable for determin-
ing the voltage VC [nodes identified with the labels Ai, i =
1 to 5, are connected to the corresponding nodes in Fig
2(d)]. Transconductors Tn1 and Tn2 are simple differential
pairs, identical to the n-channel input pair of the r-t-r
amplifier in Fig. 1(a), and are biased with an identical
tail current source [i.e., MA = MB = MBN, so that
nominally IB = I(VC) = IBn]. However, whereas the inputs
of Tn1 are fed with a differential dc voltage ±V/2 with
zero CM component, the input signal of Tn2 consists of a
differential dc voltage ±V with a non-zero CM compo-
nent Vo1 (see below), so that its bias current I turns out to
be a function of the latter. The two input differential
voltages are assumed small enough so that Tn1 and Tn2
operate in the linear region of their transfer characteris-
tics. The differential output currents of the two transcon-
ductors, which are summed in a shared load with the po-
larities indicated in Fig. 2(a), are equal to
ii
nn
=−
11
=−
where gm,n1 and gm,n2 account for the transconductance of
Tn1 and Tn2, respectively. It should be pointed out that
gm,n1 is equal to the maximum transconductance value of
the NMOS input pair of the r-t-r op-amp, while gm,n2 de-
pends on Vo1. Since the output voltage Vo1 of the current
summing section represents the input CM voltage of Tn2,
a negative feedback loop is closed. This feedback action
forces the differential output currents of Tn1 and Tn2 to be
equal which, from eq. (1), is equivalent to make gm,n2 =
gm,n1/2. In practice, Vo1 is fixed by the loop to the re-
quired value VC that brings the bias current source of Tn2
out from its saturation region, thereby reducing I to the
level I(VC) that fulfills the above equality. To account for
the loading effect caused by the two passive resistors R
in Fig. 2(d), a second gain stage connected to the output
of the current summing section has been included. CC
acts as a compensation capacitor.
The second circuit section must tune the VS shifting
value to be added to the input CM component of the r-t-r
op-amp PMOS differential pair. Basically, the same idea
as in Fig. 2(a) is followed, thus obtaining the circuit im-
plementation in Fig. 2(b), where the source-to-gate volt-
age of source follower devices MSA and MSC corre-
sponds to the shifting voltage VS. Transconductors Tp1
and Tp2 are differential pairs identical to the p-channel
input pair of the r-t-r amplifier, and are nominally biased
with the same current IBp. The output voltage Vo2 of the
section where the differential output currents of the two
transconductors are summed, controls the bias current of
the source followers and, hence, the floating voltage
sources VS. The latter are then tuned so as to make gm,p2 =
gm,p1/2, with obvious meaning of symbols (notice that the
differential input voltages of Tp1 and Tp2 are ±V/2 and
±V, respectively, whereas their input CM components are
zero and VS + VC, also respectively). Source followers
identical to MSA-MSB and MSC-MSD, biased with the
same control signal Vo2, will be used to implement the
voltage sources VS in the r-t-r op-amp.
In order to achieve a more constant small-signal be-
havior of the r-t-r amplifier input stage over the full CM
range, another simple tuning section, shown in Fig. 2(c),
is used. The target of this additional section consists in
Vg
nm
⋅
−+
1,
(1.a)
Vgii
nmnn
2
2,22
⋅
−+
(1.b)
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Shared LoadShared Load
Vi
Vi
++
Vi
Vi
−−
Input StageInput Stage
Fig. 3. Overall r-t-r op-amp topology.
Output StageOutput Stage
Vout
Vout
CF
CF
IS
IS
IS
IS
MS3MS3
MS1MS1
MS2MS2
MS4MS4
M1NM1N
M2NM2N
M1PM1PM2PM2P
MBPMBP
MBNMBN
Vout1
Vout1
VDD
VDD
VSS
VSS
MO4MO4
MO3MO3
MO2MO2
MO1MO1
MF
MF
Vo2
Vo2
VQ
VQ


VDD
VDD
VSS
VSS
MO3MO3
Vout
Vout
Vout1
Vout1
MO4MO4
MO2MO2
MO1MO1
VQ
VQ
MQ4MQ4
MQ2MQ2
MQ1MQ1
VQ
VQ
MQ3MQ3
MI2MI2
MI1MI1
IQ
IQ
MQMQ
Output StageOutput Stage
Quiescent Output Current ControlQuiescent Output Current Control
Fig. 4. Class-AB output stage (for simplicity, the compensation
network MF-CF is not shown).

making the maximum gm,n and gm,p values equal, regard-
less of any variation in fabrication process parameters
and any matching condition in the aspect ratios of the
complementary input transistors. This approach assures
an identical amplifier small-signal response for Vi,cm out-
side the common transition region. Basically, the third
block consists of two complementary differential pairs,
respectively identical to the related input pair of the r-t-r
op-amp, with a dc voltage ±V applied to their gates. Their
differential current contributions are added in a folded-
cascode summing stage. The n-channel pair is biased at
the nominal current value IB. By contrast, the bias current
of the p-channel pair (i.e., IBp) is tuned by a negative
feedback action under the control of the output voltage of
the current summing stage, so as to make gm,p equal to
gm,n. Replicas of the generated current IBp are used to bias
the p-channel pair of the amplifier input stage as well as
differential pairs Tp1 and Tp2 of the section in Fig. 2(b)
(i.e., the gates of MBP, MC, and MD are connected to Vo3).
The dc voltages ±V/2 and ±V required for the overall
operation are generated on chip by the circuit in Fig.
2(d). Although their values are process dependent, this
fact does not result critical for circuit operation, at least
with the normal tolerances of IC fabrication processes.

3. Rail-to-rail input/output video op-amp
The overall topology of the presented op-amp is
shown in Fig. 3. It consists of the constant-gm input stage
described in the previous Section along with an r-t-r
class-AB output stage. Current signal contributions of the
input pairs are added in a folded-cascode shared load.
A high-drive class-AB output stage (Fig. 4) has been
designed in order to ensure output r-t-r operation of the
op-amp. The proposed stage consists of two complemen-
tary output MOS transistors connected in common-
source configuration and provided with class-AB bias-
ing. The p-channel output device, MO1, is directly
driven by the output node of the first stage, Vout1, whereas
a level shifter is introduced in order to drive the n-
channel output device, MO2. The voltage shift amount,
which depends on the biasing current of the source fol-
lower MO3-MO4, determines the quiescent current of
the output branch. Thus, the latter can be accurately fixed
by properly tuning the biasing current of MO4 (Vout1 will
be set at the correct value by the overall feedback loop
through the r-t-r op-amp). With this goal, the shaded por-
tion in Fig. 4 has been introduced, where MQ1-MQ4 are
matched replicas of MO1-MO4, respectively. Current IQ
is forced through diode-connected transistor MQ. The
static feedback loop established by devices MQ1 to MQ4
and MI1, MI2 generates a proper shifting voltage for the
replica of the output level shifter, MQ3-MQ4, which
makes IQ to flow through MQ2. The voltage VQ gener-
ated by the static loop is used to bias the current source
of the source follower MO3-MO4 at the output stage, so
that the ensuing level shift makes a current equal to IQ to
flow through the output branch in the steady condition.
Transistors MI1-MI2 are included to produce a sign in-
version in the overall loop. Stability has to be ensured to
this feedback loop, in spite of its static nature. For this
reason, devices MI1-MI2 have been connected in a low-
gain configuration, so as to have one only high-
impedance node (drain of MQ1-MQ2) in the whole loop.
The dynamic operation of the output stage is similar to
other class-AB output stages and for this reason is not
described here. Frequency compensation of the op-amp
is achieved by means of conventional Miller technique.
As a final design consideration, it should be pointed
out that the op-amp frequency performance is not limited
by the static feedback loops used to tune the input trans-
conductance as well as the quiescent current through the
output branch. However, care has to be taken in order to
push the secondary poles introduced by the source fol-
lowers in the input and output stages to sufficiently high
frequencies.
4. Experimental results
The op-amp shown in Fig. 3 has been fabricated in
standard 0.8-µm CMOS technology, with threshold volt-
ages around 0.8 V. The circuit was designed to operate
with supply voltages of ±1.5 V, and the nominal values
of IB and IQ were set to 300 µA and 500 µA, respectively.
The small dc voltages applied to the inputs of the trans-
conductors in the tuning sections were chosen as ±V/2 =
±25 mV and, consequently, ±V = ±50 mV.
The measured dc transfer characteristic of the op-amp
in unity-gain closed-loop configuration with a 1-MΩ||15-
pF load is depicted in Fig. 5. The same behavior has been
proven with resistive loads as low as 330 Ω. Even for a
100-Ω load, the output operating range is about 2.5 V,
which is 83% of the total supply voltage.
Fig. 6 shows the total input stage transconductance
gm,tot along with the individual transconductances of the
n-channel and the p-channel input pair. The largest gm
deviations take place in the transition region, as a conse-
quence of the non-complementary shape of the individual
transconductance characteristics. Anyway, the maximum
181

Page 4

-1.50
(V)
6.25m
/div
400.m
/div
-20.0m
30.0m
-1.50
1.50
1.50
(V)
OFFSET
VOUT
400. m / div
VIN (V)

Fig. 5. Measured dc transfer characteristic of the op-amp in unity-
gain mode (solid line: output voltage, dashed line: offset voltage).

(mA/V)
-1.5-1.0-0.5 0.00.51.01.5
0.0
0.5
1.0
1.5
2.0
gm,n
gm,p
gm,tot
Vi,cm (V)

Fig. 6. Measured total transconductance
over the entire input CM range.


Fig. 7. Measured transient response for a 2.5-Vpp 1-MHz input
square wave with a 100-Ω||100-pF load (op-amp in non-
inverting unity-gain configuration).

relative error is not larger than 4.5%, which in practice is
quite a good result, especially considering that nearly
minimum size devices have been used.
The transient behavior of the op-amp in unity-gain
buffer configuration with a 100-Ω||100-pF load in re-
sponse to a 2.5-Vpp 1-MHz square wave is illustrated in
Fig. 7. In addition, Fig. 8 shows the measured THD of
the output signal for a 1-MHz input sinewave with dif-
ferent amplitudes. In the 100-Ω||100-pF load case, THD
reaches 1% for an input signal amplitude around 2.5 Vpp.
As observed, good distortion values have been obtained,
what, along with the achieved gain-bandwidth product,
constitutes a very desirable feature for video applications.
The overall measured amplifier performance is pro-
vided in Table 1 for the voltage supply and biasing cur-
rents stated above.
5. Conclusions
An r-t-r video op-amp with constant gm and class-AB
output stage has been presented. The amplifier gain-
bandwidth product is maintained substantially constant
0.00.51.01.52.0 2.53.0
-70
-60
-50
-40
1-MΩ || 15-pF
100-Ω || 100-pF
THD (dB)
Vi,pp(V)

Fig. 8. Measured THD for a 1-MHz input signal
as a function of the input amplitude.

Table 1. Summary of the measured amplifier
performance with a 1-MΩ||15-pF load
Parameter Overall amplifier
gm variation vs. Vi,cm
dc open-loop gain
Unity-gain frequency
Phase margin (simulated)
Power Consumption
Area
Noise (@ 100 kHz)
(@ 1 MHz)
CMRR|max / CMRR|min @ dc
±4.5%
83.3 dB
65 MHz
54 °
15 mW
0.35 mm
62 nV/√Hz
21 nV/√Hz
69 dB / 44 dB

2

over the entire input CM range by means of the CM re-
sponse overlapping technique. In addition, an accurate
control of the quiescent current through the output
branch is ensured. The output stage provides almost r-t-r
swing even with low-resistance loads, while high-
frequency operation is ensured thanks to the static nature
of the used feedback loops.

Acknowledgement: This work has been supported by
the Spanish R&D Plan under Grant TIC-2000-1141.
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182