Conference Paper

Constructing zero-deficiency parallel prefix adder of minimum depth

Dept. of Comput. Sci. & Eng., UCSD, La Jolla, CA, USA;
DOI: 10.1109/ASPDAC.2005.1466481 In proceeding of: Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific, Volume: 2
Source: DBLP

ABSTRACT Parallel prefix adder is a general technique for speeding up binary addition. In unit delay model, we denote the size and depth of an n-bit prefix adder C(n) as sC(n) and dC(n) respectively. Snir proved that sC(n) +dC(n) > 2n - 2 holds for arbitrary prefix adders. Hence, a prefix adder is said to be of zero-deficiency if sC(n) + dC(n) = 2n - 2, In this paper, we first propose a new architecture of zero-deficiency prefix adder dubbed Z(d), which provably has the minimal depth among all kinds of zero-deficiency prefix adders. We then design a 64-bit prefix adder Z64, which is derived from Z(d)|d=8, and compare it against several classical prefix adders of the same bit width in terms of area and delay using logical effort method. The result shows that the proposed Z(d) adder is also promising in practical VLSI design.

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    ABSTRACT: Parallel Prefix addition is a technique for improving the speed of binary addition. Due to continuing integrating intensity and the growing needs of portable devices, low-power and high-performance designs are of prime importance. The classical parallel prefix adder structures presented in the literature over the years optimize for logic depth, area, fan-out and interconnect count of logic circuits. In this paper, a new architecture for performing 32-bit Parallel Prefix addition is proposed. The proposed 32-bit prefix adder is compared with several classical adders of same bit width in terms of power, delay and number of computational nodes. The results reveal that the proposed 32-bit Parallel Prefix adder has the least power delay product when compared with its peer existing Prefix adder structures. Tanner EDA tool was used for simulating the adder designs in the TSMC 180 nm and TSMC 130 nm technologies.
    LETTERS International Journal of Recent Trends in Engineering. 12/2009; 2.
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    [Show abstract] [Hide abstract]
    ABSTRACT: Parallel Prefix addition is a technique for improving the speed of binary addition. Due to continuing integrating intensity and the growing needs of portable devices, low-power and high-performance designs are of prime importance. The classical parallel prefix adder structures presented in the literature over the years optimize for logic depth, area, fan-out and interconnect count of logic circuits. In this paper, a new architecture for performing 8-bit, 16-bit and 32-bit Parallel Prefix addition is proposed. The proposed prefix adder structures is compared with several classical adders of same bit width in terms of power, delay and number of computational nodes. The results reveal that the proposed structures have the least power delay product when compared with its peer existing Prefix adder structures. Tanner EDA tool was used for simulating the adder designs in the TSMC 180 nm and TSMC 130 nm technologies.
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: Parallel prefix addition is a technique for speeding up binary addition. Classical parallel prefix adder structures developed so far are optimized for logic depth, area, fan-out and interconnect count of logic circuits. Due to continuing integrating intensity and growing needs of portable devices, low-power and high-performance designs are of prime importance. A new technique, proposed for performing parallel prefix addition, has least power delay product in comparison with its peer prefix adder structures. Tanner EDA tool was used for simulation in TSMC 180 nm technology. Introduction VLSI Integer adders are used in arithmetic and logic units (ALU's), microprocessors and memory address-ing units. Speed of adder often decides minimum clock cycle time in a microprocessor. Parallel prefix adders (PPA) are derived from commonly known carry look ahead adders. PPA circuits use a tree network to reduce latency to 2

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