Impact of mask alignment on the tunneling field effect transistor (TFET)
ABSTRACT The tunneling field effect transistor (TFET) is a standard CMOS process flow compatible device which shows improved short channel characteristics and lower static power consumption. The device is generated by the p-implant layer overlapping the source extension. A test-structure is proposed to investigate the impact of the alignment of the p-implant mask on the device characteristics.
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ABSTRACT: The tunneling field effect transistor (TFET) is fabricated using a 65nm standard CMOS process flow. The short-narrow TFET offers an on-current of 550μA/μm which is comparable to the reference MOSFET device. Due to the integrated substrate/well contact the effective area of the TFET is smaller compared to the corresponding MOSFET. Thus, the size of a system-on-a-chip design is reduced by more than 5%. The quantum-mechanical TFET is able to extend the epoch of the CMOS technology by showing reduced short channel effects and smaller leakage currents. A multi-threshold TFET device is proposed which does not need additional implantation steps. A 0.68μm<sup>2</sup> 6 transistor memory cell is fabricated using TFETs and MOSFETs showing the compatibility of MOSFET and TFET and a decrease of the memory array area of approximately 3%.Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European; 10/2005