An efficient VLSI architecture for 2-D convolution with quadrant symmetric kernels

Abstract

A high performance digital architecture for computing 2D convolution utilizing the quadrant symmetry of the kernels is proposed in this paper. Pixels in the four quadrants of the kernel region with respect to an image pixel are considered simultaneously for computing the partial products of the convolution sum. A novel data handling strategy to identify the pixels to be fed to different processing elements helps reducing the data storage requirements in the circuitry. The new design results in 75% reduction in multipliers and 50% reduction in adders when compared with the conventional systolic architecture. The proposed architecture design is capable of performing convolution operations with 14×14 kernel at a rate of 57 1024×1024 frames per second in a Xilinx 's Virtex 2v2000ff896-4 FPGA.

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An Efficient VLSI Architecture for 2-D Convolution
with Quadrant Symmetric Kernels
Ming Z. Zhang, Hau T. Ngo, Adam R. Livingston and Vijayan K. Asari
Department of Electrical and Computer Engineering
Old Dominion University, Norfolk, VA 23529
{mzhan002, hngox001, alivi001, vasari}@odu.edu
Abstract

computing 2-D convolution utilizing the quadrant
symmetry of the kernels is proposed in this paper.
Pixels in the four quadrants of the kernel region with
respect to an image
simultaneously for computing the partial products of
the convolution sum. A novel data handling strategy to
identify the pixels to be fed to different processing
elements helps reducing the data storage requirements
in the circuitry. The new design results in 75%
reduction in multipliers and 50% reduction in adders
when compared with the conventional systolic
architecture. The proposed architecture design is
capable of performing convolution operations with
14×14 kernel at a rate of 57 1024×1024 frames per
second in a Xilinx’s Virtex 2v2000ff896-4 FPGA.
A high performance digital architecture for
pixel are considered
Keywords: 2-D convolution, symmetric kernel,
pipelined architecture, systolic architecture.
1. Introduction

frequently used operations in many image and video
processing applications. It is necessary to have optimal
design to reduce hardware
consumption and to increase high speed operation for
performing 2-D convolution
convolution is defined as:
Two dimensional convolution is one of the most
resources, power
effectively. 2-D
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where W(i, j) are the weights of a K×L kernel, I(m, n),
O(m, n) are the M×N input and output images,
respectively. Some existing designs [1-7] make use of
arbitrary coefficients for the kernels; however, we take
advantage of popular kernels with symmetric structure
and optimize to greater extend compared to
conventional approaches. In this paper, we present a
high performance systolic architecture with pipelined
delay lines to achieve high throughput rate.
2. Real Time 2-D Convolution Design
with Quadrant Symmetry

with quadrant symmetric property such as Gaussian
filters. The architecture design is based on
decomposition of (1) into (2) and (3) respectively for
odd and even dimensional kernels.
Figure 1 illustrates a specialized architecture
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Figure 1: Block diagram of the architecture for
2-D convolution with quadrant symmetric kernels
The line delays (LDs), which are implemented
with Dual Port RAMs (DPRAMs) to allow dynamic
change of image sizes, are at the front end of
Proceedings of the IEEE Computer Society Annual Symposium on VLSI
New Frontiers in VLSI Design
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processing elements (PEs) to optimize storage
requirements of delay elements. Each PE computes
partial result and passes this result to next PE where it
is summed with the partial result computed in this
current PE. 6As the pixels come in raster scan fashion
through the LDs, vertical folding takes place by adding
pixels on vertical symmetry. This folding strategy
reduces the number of adders and multipliers by half.
The results from vertical folding are then fed into K/2
horizontal delay lines of K-1 delay elements. The
architecture takes account of appropriate delays so the
results from horizontal folding are passed to
consecutive PEs correctly. Horizontal folding further
reduces the multipliers in half. At the end of PE arrays
(PEAs), the partial results are summed with adder tree
to produce 2-D convolution output at the rate of one per
cycle.
The original pixel values are also available with
K/2 more delays from the center node of the LDs. It is
very helpful that the original pixel be available in
synchronization with the output from 2-D convolution
of quadrant symmetric kernels. This synchronization
permits the subsequent processing elements to perform
their operation at run time. It also eliminates the
bottleneck of memory accesses where the pixels can be
read in without buffering the entire frame.
3. Implementation/Hardware Utilization

is performed using Xilinx’s ISE software. The FPGA
chip targeted for our implementation is a Virtex 2
2v2000ff896-4 FPGA. Gaussian filter with standard
deviation of five, in conjunction with 24×24 images is
used in verification of our design with the data
produced from MATLab software. Table 1 shows the
hardware utilization for the quadrant symmetric
architecture.
The simulation of the proposed architecture design
Table 1. Hardware utilization
Kernel CLB FF BRAM Clock Rate
10×10 695
12×12 975
14×14 1303 1900
*24×24 3664 5507
990
1407
9
11
13
23
60 MHz
60 MHz
60 MHz
59 MHz
*Compiled on XC2V8000-4

Configurable Logic Blocks (CLBs), 8% of flip-flops
(FFs), 9 embedded Block RAM modules (BRAMs).
This kernel with maximum operating frequency, which
is mainly limited by speed of 18-bit multipliers, gives
For 14×14 square kernel, it consumes 12% of
maximum throughput of 57 frames per second for
1024×1024 video frames. The architecture presented
in this paper achieves significant hardware efficiency
by reducing 75% of multipliers and nearly 50% of
adders.
4. Conclusion

high performance architecture for 2-D convolution of
quadrant symmetric filters with significant reduction
of storage requirements compared to conventional
designs. The proposed design reduces 75% of the
multipliers and nearly 50% of the adders required to
perform 2-D convolution operations. The proposed
design also provides a minimum set of delay
elements to pass the original pixel to the output in
synchronization with the convolution results. The
architecture also allows dynamic change of image
size with the constraint of maximum image size.
With a XC2V2000-4 FPGA, this design can achieve
maximum of 57 1024×1024 frames per second.
In this paper, we presented a flexible and very
5. References
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Proceedings of the IEEE Computer Society Annual Symposium on VLSI
New Frontiers in VLSI Design
0-7695-2365-X/05 $20.00 © 2005 IEEE