Conference Paper

Enhanced data retention of damascene-finFET DRAM with local channel implantation and fin surface orientation engineering

R & D Center, Samsung Electron., Yongin, South Korea
DOI: 10.1109/IEDM.2004.1419065 Conference: Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
Source: IEEE Xplore


80nm damascene-finFET (d-finFET) 512M DRAM is fabricated on bulk <100> channel directional wafer (CW). We adopted damascene technology to form the fin only to the channel region of cell array transistor with self-aligned LCI (local channel ion implantation). From the reduced contact resistance, surface treatment, and electron mobility improvement of <100> CW, 50% increased on-current is achieved in d-finFET. Utilizing LCI to d-finFET, junction leakage of the storage node has been reduced. The characteristics of d-finFET and conventional finFET (c-finFET), and <110> CW and <100> CW were compared. Using the d-finFET scheme with LCI, data retention time is further improved from the previous work of c-finFET (Lee et al., 2004).

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    • "When the current is about 3uA/cell in 90nm feature size in 1.8V operation, the current is reduced down to almost zero in 60nm in 1.2V. There have been a few reports on FinFET cell array for DRAM; FinFET cell array in sub-100nm trench capacitor DRAM [3], FinFET cell array with negative word line operation [4], and damascene FinFET cell array structure with local channel implantation scheme [5] for sub-60nm technology node. Since FinFET cell array structurally has low I off , it can achieve low V th , high I on . "
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    ABSTRACT: We fabricate local damascene FinFET cell array in sub-60nm feature sized DRAM. The local damascene structure can remove passing-gate-effects in FinFET cell array. p+ boron in-situ doped poly- silicon is chosen for the gate material, and we obtain a uniform distribution of threshold voltages at around 0.7V. Sub-threshold swing of 75mV/d and extra- polated off-state leakage current of 0.03fA are obtained, which are much suppressed values against those of recessed channel array transistors. We also obtain a few times higher on-state current. Based on the improved on- and off-state current characteristics, we expect that the FinFET cell array could be a new mainstream structure in sub-60nm DRAM devices, satisfying high density, low power, and high-speed device requirements.
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    ABSTRACT: We proposed a new p+/n+ gate locally- separated-channel (LSC) bulk FinFET which has vertically formed oxide region in the center of fin body, and device characteristics were optimized and compared with that of normal channel (NC) FinFET. Key device characteristics were investigated by changing length of n+ poly-Si gate (Ls), the material filling the trench, and the width and length of the trench at a given gate length (Lg). Using 3-dimensional simulations, we confirmed that short-channel effects were properly suppressed although the fin width was the same as that of NC device. The LSC device having the trench non-overlapped with the source/drain diffusion region showed excellent Ioff suitable for sub-50 nm DRAM cell transistors. Design of the LSC devices were performed to get reasonable Ls/Lg and channel fin width (Wcfin) at given Lgs of 30 nm, 40 nm, and 50 nm.
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    ABSTRACT: There have been concerns about how far we can extend the so far so successful conventional semiconductor memories such as DRAM, SRAM and flash memory and what is the future directions of memory development, in this article, we review the key technological limits of conventional memory scaling and the directions to overcome the problem. In addition, we review the technical challenges and opportunities of emerging new memories.
    Integrated Circuit Design and Technology, 2005. ICICDT 2005. 2005 International Conference on; 06/2005
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