Enhanced data retention of damascene-finFET DRAM with local channel implantation and fin surface orientation engineering
ABSTRACT 80nm damascene-finFET (d-finFET) 512M DRAM is fabricated on bulk <100> channel directional wafer (CW). We adopted damascene technology to form the fin only to the channel region of cell array transistor with self-aligned LCI (local channel ion implantation). From the reduced contact resistance, surface treatment, and electron mobility improvement of <100> CW, 50% increased on-current is achieved in d-finFET. Utilizing LCI to d-finFET, junction leakage of the storage node has been reduced. The characteristics of d-finFET and conventional finFET (c-finFET), and <110> CW and <100> CW were compared. Using the d-finFET scheme with LCI, data retention time is further improved from the previous work of c-finFET (Lee et al., 2004).
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ABSTRACT: We proposed a new p<sup>+</sup>/n<sup>+</sup> poly-Si gate bulk fin-type field-effect transistor that has two channel fins separated locally by a shallow trench filled with oxide or p<sup>+</sup> polygate. Key device characteristics were investigated by changing the n<sup>+</sup> poly-Si gate length La, the material filling the trench, and the width and length of the trench at a given gate length L<sub>g</sub>. It was shown that the trench filled with p<sup>+</sup> poly-Si gate should not be contacted with the source/drain diffusion region to achieve an excellent I<sub>on</sub>/I<sub>off</sub> (> 1010) that is suitable for sub-50-nm dynamic random access memory cell transistors. Based on the aforementioned device structure, we designed reasonable Ls/Lg and channel fin width W<sub>cfin</sub> at given L<sub>g</sub> 's of 30, 40, and 50 nm.IEEE Electron Device Letters 01/2008; · 2.79 Impact Factor
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ABSTRACT: We have experimentally analyzed the leakage mechanism and device degradations caused by the Fowler-Nordheim (F-N) and hot carrier stresses for the recently developed dynamic random-access memory cell transistors with deeply recessed channels. We have identified the important differences in the leakage mechanism between saddle fin (S-Fin) and recess channel array transistor (RCAT). These devices have their own respective structural benefits with regard to leakage current. Therefore, we suggest guidelines with respect to the optimal device structures such that they have the advantages of both S-Fin and RCAT structures. With these guidelines, we propose a new recess-FinFET structure that can be realized by feasible manufacturing process steps. The structure has the side-gate form only in the bottom channel region. This enhances the characteristics of the threshold voltage (V<sub>TH</sub>), ON/OFF currents, and the retention time distributions compared with the S-Fin structure introduced recently.IEEE Transactions on Electron Devices 01/2008; · 2.06 Impact Factor
Conference Paper: Challenges for the DRAM cell scaling to 40nm[Show abstract] [Hide abstract]
ABSTRACT: This paper reviews the concepts, status and challenges for the DRAM scaling down to 40nm. The technologies that are discussed are the DRAM cell capacitor structures and materials, as well as the cell transistor structuresElectron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006