Conference Paper

Analysis of the effect of LUT size on FPGA area and delay using theoretical derivations

Inst. of Microelectron., Xidian Univ., China
DOI: 10.1109/ISQED.2005.20 Conference: Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on
Source: IEEE Xplore

ABSTRACT Based on architecture analysis of island-style FPGA, area and delay models of LUT FPGA are proposed. The effect of LUT size on FPGA area and performance is studied. Results show optimal LUT size conclusion from computation models is the same as that of experiments. A LUT size of 4 produces the best area results. A LUT size of 5 provides the better performance.


Available from: Yintang Yang, May 12, 2015
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