Analysis of the effect of LUT size on FPGA area and delay using theoretical derivations
ABSTRACT Based on architecture analysis of island-style FPGA, area and delay models of LUT FPGA are proposed. The effect of LUT size on FPGA area and performance is studied. Results show optimal LUT size conclusion from computation models is the same as that of experiments. A LUT size of 4 produces the best area results. A LUT size of 5 provides the better performance.
Full-textDOI: · Available from: Yintang Yang, May 12, 2015
Conference Paper: The effect of LUT size on nanometer FPGA architecture[Show abstract] [Hide abstract]
ABSTRACT: In this paper, the effect of the LUT size on the FPGA area and delay with the recent progress of the semiconductor technology is investigated. An optimized routing area and delay modelling in FPGA architecture with nanometer process is proposed. The proposed method has advantage on accuracy over the previous modelling, due to different spacings for nanometer process. With the improved modelling, we determine the best LUT size in terms of FPGA area and delay by a CAD flow including ABC, Hspice, T-Vpack and VPR. The experimental results show that 6-LUT provides the best area-delay product for a nanometer FPGA.Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on; 01/2012
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ABSTRACT: A synthesis flow oriented on producing the delay-insensitive dual-rail asynchronous logic is proposed. Within this flow, the existing synchronous logic synthesis tools are exploited to design technology independent single-rail synchronous Boolean network of complex (AND-OR) nodes. Next, the transformation into a dual-rail Boolean network is done. Each node is minimized under the formulated constraint to ensure hazard-free implementation. Then the technology dependent mapping procedure is applied. The MCNC and ISCAS benchmark sets are processed and the area overhead with respect to the synchronous implementation is evaluated. The implementations of the asynchronous logic obtained using the proposed (with AND-OR nodes) and the state-of-the-art (nodes are designed based on DIMS, direct logic and NCL) network structures are compared. A method, where nodes are designed as simple (NAND, NOR, etc.) gates is chosen for a detailed comparison. In our approach, the number of completion detection logic inputs is reduced significantly, since the number of nodes that should be supplied with the completion detection is less than in the case of the network structure that is based on simple gates. As a result, the improvement in sense of the total complexity and performance is obtained.Integration the VLSI Journal 01/2014; 47(1):148–159. DOI:10.1016/j.vlsi.2013.02.002 · 0.53 Impact Factor
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ABSTRACT: This paper presents an analytical model that relates the ar- chitectural parameters of an FPGA to the place-and-route runtimes of the FPGA CAD tools. We consider both a sim- ulated annealing based placement algorithm employing a bounding-box wirelength cost function, and a negotiation- based A* router. We also show an example application of the model in early architecture evaluation.