Analysis of the effect of LUT size on FPGA area and delay using theoretical derivations
ABSTRACT Based on architecture analysis of island-style FPGA, area and delay models of LUT FPGA are proposed. The effect of LUT size on FPGA area and performance is studied. Results show optimal LUT size conclusion from computation models is the same as that of experiments. A LUT size of 4 produces the best area results. A LUT size of 5 provides the better performance.
- SourceAvailable from: Dilip K. Banerji
Conference Proceeding: Routability Prediction for Hierarchical FPGAs.[show abstract] [hide abstract]
ABSTRACT: This paper investigates the problem of routability prediction in a FPGA that employs a hierarchical routing architecture. Such a FPGA is called a hierarchical FPGA (HFPGA). A novel model is proposed to analyze various HFPGA configurations. A software tool has been developed to predict the routability of circuits on specific HFPGA architectures. Primary contribution of this work is that routability prediction can be done immediately after the technology-mapping step, rather than after placement. The effect of connection block and switch block flexibility on routability is also studied. The results show that compared to a symmetrical FPGA architecture we can achieve the same degree of routability on a HFPGA, with much fewer routing switches9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA; 01/1999
- [show abstract] [hide abstract]
ABSTRACT: In this paper we revisit the FPGA architectural issue of the effect of logic block functionality on FPGA performance and density. In particular, in the context of lookup table, cluster-based island-style FPGAs  we look at the effect of lookup table (LUT) size and cluster size (number of LUTs per cluster) on the speedand logic density of an FPGA. Although this question was addressed some time ago in      and , several reasons compelled us to revisit the issue. First, prior work focused on non-clustered logic blocks, which are known to have a significant impact on the area and delay . Second, most prior studies tended to look at area or delay, but not both as we will here. Third, prior results were based on IC process generations that are several factors larger than current process generations, and so do not take deep-submicron electrical effects into account. In the present work, we perform detailed spice-level simulations of circuits and perform appropri...IEEE Transactions on Very Large Scale Integration (VLSI) Systems 04/2000; · 1.22 Impact Factor