Conference Paper

Analysis of the effect of LUT size on FPGA area and delay using theoretical derivations

Inst. of Microelectron., Xidian Univ., China
DOI: 10.1109/ISQED.2005.20 Conference: Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on
Source: IEEE Xplore


Based on architecture analysis of island-style FPGA, area and delay models of LUT FPGA are proposed. The effect of LUT size on FPGA area and performance is studied. Results show optimal LUT size conclusion from computation models is the same as that of experiments. A LUT size of 4 produces the best area results. A LUT size of 5 provides the better performance.

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    • "The relationship between logic block architecture and area efficiency was described in [5] [6]. The model in [6] also takes into account cluster-based FPGAs and cluster architecture . "
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    ABSTRACT: This paper presents an analytical model that relates the ar- chitectural parameters of an FPGA to the place-and-route runtimes of the FPGA CAD tools. We consider both a sim- ulated annealing based placement algorithm employing a bounding-box wirelength cost function, and a negotiation- based A* router. We also show an example application of the model in early architecture evaluation.
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    • "There has also been work providing early stage delay values for FPGAs by Manohararajah [19], which uses a lookup table with pre-recorded values of interconnect delays as a function of architecture parameters. The previous work closest to ours is by Gao et al, who relates LUT size to area as well as depth of forming N -LUTs for a non-clustered FPGA [20]. We present a more complete model that considers cluster-based architectures (which are more representative of real FPGAs), and we model a wider range of architectural parameters. "
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    ABSTRACT: This paper presents an analytical model that relates FPGA architectural parameters to the logic size and depth of an FPGA implementation. In particular, the model relates the lookup-table size, the cluster size, and the number of inputs per cluster to the amount of logic that can be packed into each lookup-table and cluster, the number of used inputs per cluster, and the depth of the circuit after technology mapping and clustering. Comparison to experimental results shows that our model has good accuracy. We illustrate how the model can be used in FPGA architectural investigations to complement the experimental approach. The model's accuracy, combined with the simple form of the equations, make them a powerful tool for FPGA architects to better understand and guide the development of future FPGA architectures.
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    • "A similar problem has been encountered in the design of the FPGA fabrics, when deciding for the optimum look-up tables (LUT) size [Gao, 2005]. It has been found that implementing the design using 4-or 5-input LUTs brings most benefits. "
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    ABSTRACT: A novel synthesis method of a dual-rail asynchronous multi-level logic is proposed. The logic is implemented as a monotonous multi-level network of minimized AND-OR nodes together with the completion detection logic. Each node is a hazard-free structure. It is achieved based on the product term minimization constraint that the authors have formulated and proved in their previous paper. The MCNC and ISCAS benchmark sets were processed and the area overhead with respect to the synchronous implementation was evaluated. Then the implementation complexity of the proposed method and a state-of-the-art method based on the duplication of every gate was compared. A considerable improvement was obtained.
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