Conference Paper

Tri-scan: a novel DFT technique for CMOS path delay fault testing

Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
DOI: 10.1109/TEST.2004.1387386 Conference: Test Conference, 2004. Proceedings. ITC 2004. International
Source: DBLP


We propose a novel design for testability technique to apply two pattern tests for path delay fault testing. Due to stringent timing requirements of deep-submicron VLSI chips, design-for-test schemes have to be tailored for detecting stuck-at as well as delay faults quickly and efficiently. Existing techniques such as enhanced scan add substantial hardware overhead, whereas techniques such as scan-shifting or functional justification make the test generation process complex and produce lower coverage for scan based designs as compared to non-scan designs. We exploit the characteristics of CMOS circuitry to enable the application of two-pattern tests. The proposed technique reduces the problem of path delay fault testing for scan based designs to that of path delay fault testing with complete accessibility to the combinational logic, and has minimal area overhead. The scheme also provides significant reduction in power during scan operation.

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