Conference Paper

Tri-scan: a novel DFT technique for CMOS path delay fault testing

Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA;
DOI: 10.1109/TEST.2004.1387386 Conference: Test Conference, 2004. Proceedings. ITC 2004. International
Source: DBLP

ABSTRACT We propose a novel design for testability technique to apply two pattern tests for path delay fault testing. Due to stringent timing requirements of deep-submicron VLSI chips, design-for-test schemes have to be tailored for detecting stuck-at as well as delay faults quickly and efficiently. Existing techniques such as enhanced scan add substantial hardware overhead, whereas techniques such as scan-shifting or functional justification make the test generation process complex and produce lower coverage for scan based designs as compared to non-scan designs. We exploit the characteristics of CMOS circuitry to enable the application of two-pattern tests. The proposed technique reduces the problem of path delay fault testing for scan based designs to that of path delay fault testing with complete accessibility to the combinational logic, and has minimal area overhead. The scheme also provides significant reduction in power during scan operation.

0 Bookmarks
 · 
154 Views
  • [Show abstract] [Hide abstract]
    ABSTRACT: We present techniques for response analysis for timing characterization, i.e., delay test and debug of Integrated Circuits (ICs), using on-chip delay measurement of critical paths of the IC. Delay fault are a major source of failure in modern ICs designed in Deep Sub-micron technologies, making it imperative to perform delay fault testing on such ICs. Delay fault testing schemes should enable detection of gross as well as small delay faults in such ICs to be efficient. Additionally there is a need for performing efficient and systematic silicon debug for timing related failures. The timing characterization techniques presented in this paper overcome the observability limitations of existing timing characterization schemes in achieving the aforementioned goals, thus enabling quick and efficient timing characterization of DSM ICs. Additionally the schemes have low hardware overhead and are robust in face of process variations.
    Journal of Electronic Testing 01/2010; 26:599-619. · 0.45 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: Delay testing has become a major issue for manufacturing advanced systems on a chip. Automatic test equipment and scan techniques are usually applied in delay testing. However, the circuits under test have many circuit paths and dependent input patterns; it is hard to measure delay times accurately, especially when debugging small delay defects. We propose a built-in delay measurement (BIDM) circuit that is modified from Vernier delay lines. All digitally designed BIDMs with small area overhead can be easily embedded within testing circuits. BIDMs can be used to record the data propagation delay times within circuit path segments, for delay testing, diagnosis, and calibration requirements internal to the chip. Our BIDM was implemented in a 32bit error correction circuit by a chip using TSMC 0.18u technology. The instruments measured results showing that the BIDM chip correctly reported the CUT segment path delay times. The chip measurement results were a 95.83% match to the postlayout SPICE simulation values. This BIDM makes it possible to debug small delay defects in chips.
    VLSI Test Symposium, 2008. VTS 2008. 26th IEEE; 01/2008
  • Journal of Systems Engineering and Electronics - J SYST ENG ELECTRON. 01/2007; 18(1):40-44.

Full-text

View
0 Downloads
Available from