Conference Paper

A Probabilistic Framework to Estimate Full-Chip Subthreshold Leakage Power Distribution Considering Within-Die and Die-to-Die P-T-V Variations

University of California, Santa Barbara, CA
DOI: 10.1109/LPE.2004.240888 Conference: Low Power Electronics and Design, 2004. ISLPED '04. Proceedings of the 2004 International Symposium on
Source: IEEE Xplore

ABSTRACT This paper presents a probabilistic framework for full-chip estimation of subthreshold leakage power distribution considering both within-die and die-to-die variations in process (P), temperature (T) and supply voltage (V). The results obtained under this framework are compared to BSIM results and are found to be more accurate in comparison to those obtained from existing statistical models. Using this framework, a quantitative analysis of the relative sensitivities of subthreshold leakage to P-T-V variations has been presented. For the first time, the effects of die-to-die channel length and temperature variations on subthreshold leakage are studied in combination with all within-die variations. It has been shown that for accurate estimation of subthreshold leakage, it is important to consider die-to-die temperature variations which can significantly increase the leakage power due to electrothermal couplings between power and temperature. Furthermore, the full-chip leakage power distribution arising due to both within-die and die-to-die P-T-V is calculated, which is subsequently used to estimate the leakage constrained yield under the impact of these variations. The calculations show that the yield is significantly lowered under the impact of within-die and die-to-die process and temperature variations.

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