Page 1

A Probabilistic Framework to Estimate Full-Chip

Subthreshold Leakage Power Distribution Considering

Within-Die and Die-to-Die P-T-V Variations

Songqing Zhang, Vineet Wason and Kaustav Banerjee

Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106

{szhang, vwason, kaustav}@ece.ucsb.edu

ABSTRACT

This paper presents a probabilistic framework for full-chip estima-

tion of subthreshold leakage power distribution considering both

within-die and die-to-die variations in process (P), temperature (T)

and supply voltage (V). The results obtained under this framework

are compared to BSIM results and are found to be more accurate in

comparison to those obtained from existing statistical models. Us-

ing this framework, a quantitative analysis of the relative sensitivi-

ties of subthreshold leakage to P-T-V variations has been presented.

For the first time, the effects of die-to-die channel length and tem-

perature variations on subthreshold leakage are studied in combina-

tion with all within-die variations. It has been shown that for accu-

rate estimation of subthreshold leakage, it is important to consider

die-to-die temperature variations which can significantly increase

the leakage power due to electrothermal couplings between power

and temperature. Furthermore, the full-chip leakage power distribu-

tion arising due to both within-die and die-to-die P-T-V is calcu-

lated, which is subsequently used to estimate the leakage con-

strained yield under the impact of these variations. The calculations

show that the yield is significantly lowered under the impact of

within-die and die-to-die process and temperature variations.

Categories and Subject Descriptors

B.7.1 [Integrated Circuits]: Types and Design Styles – VLSI.

General Terms: Performance, Design.

Keywords: Subthreshold leakage power distribution, yield

estimation, process variations, die-to-die variations, within-die

variations, electrothermal couplings.

1. INTRODUCTION

For sub-100 nm CMOS technologies, within-die and die-to-die

variations in process (P), supply voltage (V) and temperature (T)

are resulting in an increasing spread in the distribution of perform-

ance metrics such as delay, power, robustness and reliability. In

particular, leakage power that constitutes an increasing component

of total power has been reported to have 20X variations for a 180

nm CMOS technology [1]. Thus, designing with the worst-case

leakage values may result in excessive guard-banding while under-

estimating the leakage might result in highly optimistic designs.

Therefore, in the present scenario, probabilistic modeling is more

meaningful in comparison to a deterministic analysis. Additionally,

due to a 5X increase of total leakage power every generation [2],

the design constraint based on leakage power may soon limit the

yield. Therefore, it is critical to develop a probabilistic framework

for accurately estimating full-chip subthreshold leakage power

distribution under P-T-V variations which can be subsequently

used to accurately estimate the yield. Furthermore, a quantitative

analysis of the relative sensitivities of leakage to P-T-V variations

is highly desirable so that relevant variations can be targeted to

improve the yield.

Although, existing work [3] has successfully quantified the im-

pact of parameter variations on performance, but there is no known

work that has sufficiently described the combined effects of P-T-V

variations on leakage power. Su et al. [4] estimated the full chip

leakage considering uneven voltage drop and uneven temperature

but it is not a probabilistic approach and hence can’t be used for

estimating yield. Recently, Rao et al. [5] studied the impact of

channel length variations on subthreshold leakage, but their analy-

sis was based on an empirical relationship between leakage and

channel length which cannot be easily extended to other variations

such as oxide thickness or temperature variations since that would

first require an empirical and invertible relationship between leak-

age and oxide thickness or temperature. Although, the work pre-

sented in [6]-[8] develop statistical models to estimate the leakage

under variations, but they do not account for the combined effects

of within-die and die-to-die P-T-V variations. For instance, Naren-

dra et al. [7] analyzed the impact of only within-die Vth variation on

subthreshold leakage whereas Mukhopadhyay et al. [6] analyzed

the sensitivity of various leakage components to within-die process

and voltage variations only. Also, Srivastava et al. [8] analyzed the

impact of only within-die process variations. Moreover, due to the

approximations involved, these analyses are inaccurate when com-

pared to BSIM models as will be discussed later in the paper. Also,

these models cannot be used to estimate the yield since they do not

provide the probability distribution function of the leakage power.

In this paper, a probabilistic framework to simultaneously ana-

lyze the impact of both within-die and die-to-die P-T-V variations

on subthreshold leakage power for sub-100 nm CMOS technolo-

gies has been introduced. We focus on subthreshold leakage since

it is the most dominant component of total leakage in high-

performance ICs [9]-[10]. Moreover, as compared to other leakage

components namely gate leakage and BTBT leakage [11]-[12], it is

most sensitive to parameter variations [12] because of its exponen-

tial dependence on effective channel length and temperature [12] -

[14]. The analytical models presented under this framework are

compared to BSIM models and are found to be more accurate as

compared to existing statistical models [7]-[8]. We show in this

paper that for accurate estimation of full-chip subthreshold leakage,

it is important to consider die-to-die temperature variations which

can significantly increase the leakage power due to electrothermal

couplings involved between power and temperature [14]. Thus,

temperature and power have been self-consistently evaluated to

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5.4

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account for these couplings. Furthermore, the full-chip leakage

power distribution arising due to both within-die and die-to-die P-

T-V variations is calculated, which is subsequently used to estimate

the leakage constrained yield under the impact of these variations.

The paper is organized as follows: In section 2, we present a

mathematical framework to analyze the impact of single and multi-

parameter variations. This framework is used to study the impact of

within-die and die-to-die variations on subthreshold leakage in

Sections 3 and 4. In Section 5, the leakage-constrained yield is

estimated under the impact of variations. Concluding remarks are

made in Section 6.

2. MATHEMATICAL PROBLEM FORMULATION

The electrical performance of a circuit is a function of environ-

mental factors such as supply voltage (Vdd), temperature (T) etc.,

and physical parameters such as channel length (L), oxide thickness

(tox) etc. This dependence of electrical performance (y) can be rep-

resented by y=g(x1 ,x2 ... xn), where x1, x2 ... xn are random vari-

ables representing the variations in above parameters. The nominal

value (ηy), mean value (µy) and variance (σy) of y can be expressed

as (1)-(3):

(

n xxxy

gn

µµµ

...,

21

=

)

(1)

( ) (

p

)

∫

min

n

∫

min

1

x

=

max

n

max

1

x

......, ..., ...

12121

x

x

nnny

dx dxxxxxxxg

µ

(2)

()

()

()

max

n

x

∫

max

1

x

∫

min

n

x

min

1

x

2

2

y

12121

..., ..., ... ...

nynn

g x xx p x xx dx dx

σµ=−

(3)

In the above equations, µx1 , µx2 ... µxn represent the mean and

p(x1 ,x2 ... xn) represents the joint probability density function

(p.d.f.) of random variables x1, x2 ... xn. In addition to the above

parameters, we are interested in delta (δ) and spread (s) defined as:

n

yy

y

δ

and

n

y

−

=µ

2

2

y

2

y

y

n

S

σ

=

(4)

The parameter delta indicates a normalized increase while the

spread indicates a normalized variance of y. The analysis presented

in this paper assumes Gaussian distributions for x1, x2 ... xn which

is supported by experimental observations [15]. In the next subsec-

tion, a mathematical framework to model the fluctuations in y un-

der Gaussian variations in a single parameter is first presented.

Next, a few functions (y = g(x)) relevant for our work have been

analyzed under this framework (Table 1.) Subsequently, a frame-

work to extend this methodology for independent multivariate

Gaussian parameter variations is presented.

2.1. Single Gaussian Parameter Variation

Given a function y=g(x), the mean of y can be expressed as:

( )

,

( )

y

g x fx dx

µ σ

µ

−∞

where fµ,σ (x), µ and σ represent the p.d.f., mean and variance of x.

Applying Taylor’s theorem, we get:

(

0

!

n

n

=

−∞

Equation (6) can be simplified as:

2

2!

k

k

=

+∞

=∫

(5)

( )( )

) ( )

x dx

,

n

n

y

g

xf

µ σ

µ

µµ

+∞

∫

+∞

∑

=−

(6)

()( )

k

()( )

!

k

2

2

01

2

k kn

kk

yy

k

k

gg

n

µµ

µσσ

+∞

∑

+∞

∑

=

==+

(7)

By neglecting higher order terms in (7), we get:

( ) ( )

2

2

''

yy

y

y

n

gg

s

n

µ

µµ

δ

−

==

(8)

From the above equation, it can be observed that the sign of δ

depends on the second derivative of g(x). A positive δ indicates an

average increase in the parameter y. Table 1 below lists delta for

different functions g(x) that will be used in the later sections.

Table 1: δy for y = g(x) assuming Gaussian distribution for

random variable x (with spread S).

y= g(x)

Delta (δy)

µ

βx

aey =

1

2

2

2

−=

S

y

e

β

δ

µ

βx

−

e

x

A

y

=

(

1

)

1

2

2

2

2

−+≈

⋅S

y

eS

β

βδ

, see note 1

2.2. Multiple Gaussian Parameter Variation

In a manufacturing process, process variations can be expressed

in terms of variations in parameters such as L, tox, Vdd, T etc. If

these parameters are determined at different steps of the manufac-

turing process, they can be assumed to be statistically independent

[15]. In this case, we assume that these Gaussian variables are per-

fectly uncorrelated. If the function y=g(x1 ,x2 ... xn) can be ex-

pressed in a variable separable form, expression for δ can be easily

evaluated. For instance, if y can be expressed as a product of indi-

vidual functions g(xi) i.e. if

( )

1

i

=

Equation (9) is used in Section 3 for calculating δy under multi-

variable parameter variations.

()

1

11

[]

i

nn

iiyg

i

y g xthen

δδ

=

==+−

∏∏

(9)

3. ANALYSIS

UNDER WITHIN-DIE PARAMETER VARIATIONS

3.1. Calculation of Delta for Ids

The subthreshold leakage current for a MOSFET can be modeled

as [13]:

OF SUBTHRESHOLD LEAKAGE

()

()

2

11

gs

mV

th

TT

VV

eff

Vds V

dseff oxT

eff

W

L

ICm V ee

µ

−

−

=−−

0

gs

mV

th

T

VV

eff

s

eff

W

L

Ie

−

≈

where

ox

Ba si

C

qN

m

ψ

4

ε

1+=

(10)

Here, µeff is the effective mobility, Cox is the gate-oxide capacitance,

Leff is the effective channel length, Weff is the effective width, VT is

the thermal voltage, Na is the channel doping concentration and ψB

is the difference between the Fermi potential and the intrinsic po-

tential. Since

eff

T

µ∝

and

T

V

∝

sentially be assumed temperature independent [13]. In other words,

it can be regarded as a technology parameter, independent of device

parameters such as effective channel length, supply voltage, and

temperature. Now, for small variations in channel length, threshold

1.5

−

T

, Is0 in equation (10) can es-

1 Both functions are only valid within 3σ range around the mean value.

The result is an approximation obtained by applying Talyor expansion on

the 1/x term, preserving only first two terms, and integrating x over 3σ

range of the random variation.

157

Page 3

voltage (Vth) can be assumed to be linear around nominal value of

channel length (ηLeff) and can be expressed as:

eff

eff

eff

ththL

L

L

VV

β

η

∆

=−

(11)

where

and βLeff is a constant for a device (NMOS/PMOS) defined as:

th

V is the nominal value of threshold voltage, ∆Leff=ηLeff -Leff

eff

eff

L

th

L

Teff

dV

mV dL

η

β

=

(12)

Using (10) and (11), we can write,

eff

Leff

Leff

L

ds

eff

A

Ie

L

β

η

−

=

, where

0

gs

mV

th

Leff

T

VV

s eff

A I W e

β

−

+

=

(13)

We can now apply the result from Table 1 and calculate delta of

leakage due to Leff variation as:

(

1

DS eff

IL

)

2

Leff

2

Leff

2

L

2

1

eff

S

Se

β

δβ≈+⋅−

(14)

where SLeff is the spread in channel length. Thus using (14), we can

easily calculate the increase in subthreshold leakage current due to

within-die channel length variations. The only unknown in (14)

βLeff , which is a critical parameter, will be estimated in the next

section. The model presented above for calculating subthreshold

leakage increase is simple but still accurate since BSIM equations

are used to derive βLeff .

3.2. Calculation of β

Analytically, βLeff can be calculated using (12). The calculation

of β for other variables such as T, tox and Vdd can be done using

equations similar to (12). The threshold voltage (Vth) in (12) can be

expressed as [10], [13], [16]:

()(

HALOV BODYVVV

th th thth0

∆+∆+=

The fringe field effects and narrow-width effects have been ignored

in (15). Vertical non-uniform doping (retrograde doping) is used to

increase threshold voltage and it is considered a part of Vth0.

∆Vth(BODY) and ∆Vth(HALO) are independent of effective channel

length whereas ∆Vth(SCE, DIBL) is exponentially dependent on

channel length [13]:

)()

DIBL SCEV

th

,

∆−

(15)

()()

22

,22

eff

L

eff

L

tt

LL

th bis DS

V SCE DIBLVVee

⎛

⎜

⎜

⎝

⎞

⎟

⎟

⎟

⎠

⎡

⎣

⎤

⎦⎜

∆= −Φ+⋅+

(16)

From (15) and (16), it can be observed that as effective channel

length scales down, β defined by (12) grows exponentially thus

significantly increasing the leakage. Because of an exponential

dependence of

DS

equations are used to get an accurate estimate. We first use BPTM

parameters [17] and BSIM3.2 equations [16] to calculate Vth as a

function of Leff, and (12) is then used to evaluate β. It was found β

varies over a small range as shown in Figure 1. Hence, BSIM equa-

tions are used to calculate

DS

length spread which is then curve-fitted with (14) to calculate an

average value of β. Curve fitting allows us to consider the fact that

β is slightly higher when effective channel length is shorter than

normal, and transistors with shorter effective channel length con-

tribute more to total leakage than transistors with longer effective

channel length. In the above analysis, we have used BPTM [17]

parameters for 100 nm (VDS=1.2V, Tnom=300K, Leff=60nm). It is

shown in Section 3.3 that calculating β by above methodology and

I δ

on β, the value of β is critical and hence BSIM

I δ

as a function of effective channel

inserting its value in (14) gives results similar to those predicted by

BSIM models.

54

56

Mean Channel Length (nm)

5860 6264

66

4

5

6

7

8

9

10

11

β

NMOS

PMOS

300310 320330 340 350

Temperature (K)

360370

-15.0

-14.5

-14.0

-13.5

-13.0

-12.5

-12.0

-11.5

-11.0

-10.5

β

NMOS

PMOS

β

1.10 1.15 1.20 1.25 1.30

Supply Voltage (V)

-2.52

-2.48

-2.44

-2.40

β

-2.36

NMOS

PMOS

Figure 1: Variation of β with Leff, T, tox and Vdd.

3.3. Comparison with Existing Statistical Models

In this section, we compare the results obtained under the pro-

posed framework with those obtained from existing statistical mod-

els and BSIM model. The methodologies described in [7]-[8] are

compared based on (13). Equation (17) is used to calculate the

subthreshold leakage increase based on BSIM model, which as-

sumes Gaussian variation for channel length

2

()

2

3

2

3

1

a

1

πσ

µ

. ( ).

L

2

1

( )

L

DS

SUB

I

SUB

Ie dL

I

µ

µσ

σ

µσ

δ

−−

+

∫

−

=−

(17a)

where

2

()

2

3

2

3

1

πσ

2

L

ae dL

µ

µσ

σ

µσ

−−

+

∫

−

=

(17b)

In the above equation, ISUB(L) is the subthreshold leakage current

estimated using BSIM equations [16], µ and σ being the mean and

the variance of the channel length. In this work, ISUB(L) is calcu-

lated by porting BSIM3.2 equation into MATLAB so that Vth, Ids

and other parameters can be easily calculated based on BSIM pa-

rameters.

Table 2: Comparison with existing statistical models

Model

DS

I δ

Our Model

()

2

2

Leff

2

L

2

11

Leff

DSeff eff

S

IL

Se

β

δβ≈+⋅−

Narendra et al. [7]

2

2

2

1

Leff

DS

S

S

I

e

β

δ=−

Srivastava et al. [8]

222

L

2

22

DSeffeff

IL

SS

δββ=++

Table 2 above summarizes the increase in subthreshold leakage

predicted by our model and the existing models [7]-[8]. Figure 2

plots the percentage increase in subthreshold leakage as a function

of spread in channel length. Also, the increase in leakage estimated

by BSIM models is plotted. The expression for [7] was derived by

analyzing their Ids model under our methodology, while the expres-

sion for [8] was derived by using the mean values for Ids presented

in [8]. It can be seen that our model compares well with BSIM

model in the region of interest. On the other hand, Narendra et al.

[7] underestimates the increase in leakage since it neglects the 1/Leff

pre-factor in (13). Srivastava et al. [8] overestimates the leakage

158

Page 4

since it uses a Taylor series approximation for calculation of mean.

It should be noted that since curve fitted values of β are used while

comparing [7], results obtained under [7] will appear even worse if

nominal values of β are used. This is because, the curve-fitting of β

allows us to consider the variations in β which have been ignored

in [7]-[8]. The model presented in [6] involves a large number of

parameters and unlike (14), the expressions derived in [6] do not

give a clear insight on the impact of variations on leakage. For

instance, (14) clearly shows that variations result in an increase of

leakage which cannot be easily discerned from [6].

eff

L

S

Figure 2: Percentage increase in leakage plotted for different val-

ues of

eff

The subthreshold leakage for a PMOS has stronger dependence

on channel length variation as compared to an NMOS as shown in

Figure 3. This is because of the fact that NMOS has β of 5.2 as

compared to a β of 10 for PMOS at 100 nm technology node. This

is due to a steeper Vth roll off slope for PMOS than for NMOS [16].

L S

(for NMOS) predicted by different models.

Channel Length Spread (

0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

20

30

40

50

60

eff

L

S

)

10

0

0.0

BSIM3.2, NMOS

Our Model, NMOS

BSIM3.2, PMOS

Our Model, PMOS

Figure 3: Percentage increase in leakage plotted for different val-

ues of

eff

3.4. Considering all Within-Die Variations

In addition to within-die channel length variation, we take into

account within-die gate oxide thickness (tox), supply voltage (Vdd)

and temperature (T) variations and assume them to be independent.

Considering these variations, we can rewrite (10) as:

L S

for NMOS and PMOS at 300K.

: . .

X r v

0

0

: . .

X r v

1

gs

mV

th eff

LX

eff

T

eff

eff

gs

mV

th

Leff

X

eff

T

VVL

X

XL

eff

dss

eff

L

VV

X

X

L

s eff

eff

W

L

IIe

I W eee

L

ββ

β

β

−∆

∆

−−

∆

−

∆

−

−

−

∑

=

⎛

⎜

⎜

⎝

⎞

⎟

⎟

⎛

⎜

⎝

⎞

⎟

⎠

=

⎠∏

(18)

Here, X represents the random variable for different parameters

such as Tox, T, and Vdd, X represents its nominal value,

XX

η∆=−

and

X

β is a constant defined in (19). Here again,

threshold voltage (Vth) is assumed to vary linearly around the

nominal value of X.

η

β =

X

thX

X

T

dV

dX mV

(19)

Using (9), we can calculate the delta of the leakage current as:

(

1

ds effeff

ILL

S

⎢

⎣

)

()

2

Leff

2

X

2

L

2

X

2

Leff

2

X

2

L

2

X

2

22

: . . X r v

2

L

22

: .

1

111

eff

eff

eff eff

SS

SS

L

X r v

ee

See

β

β

β

β

δβ

β

⎡

⎢

⎤

⎥

⎥

⎦

⎛

⎜

⎜

⎝

⎞

⎟

⎟

⎠

≈+⋅−

⎛

⎜

⎜

⎝

⎞

⎟

⎟

⎠

≈+⋅ − +−

∏

∑

(20)

According to ITRS 2003 [10], the effective channel length

spread and gate oxide thickness spread are projected to stay at

3σ=10% and 3% respectively. From [4], we get an estimate of

within-die supply voltage and within-die temperature variations,

and choose supply voltage spread to be 3σ=5% and temperature

spread to be 3σ=3% (3σ corresponds to 12K variation at a nominal

value of 400K). Assuming above variations, Figures 4 and 5 plot β

and δ for NMOS as well as PMOS. βX is evaluated by a similar

approach as in Section 3.2.

Note that threshold voltage is dependent on supply voltage varia-

tions through body effect. It can be observed that the impact of

channel length and temperature variations is much greater than

other variations. However, it is apparent from (20) that all of those

variations serve to increase the total subthreshold leakage. In this

analysis, we assumed that within-die temperature variations are

uncorrelated with other within-die process variations, which is

reasonable as long as within-die temperature gradient is determined

from layout of different components in the die [4].

βX

Figure 4: β for different within-die variations for NMOS and

PMOS for 100 nm device at 300K.

159

Page 5

δ

DS

I

Figure 5: δ for leakage contributed by different within-die varia-

tions for NMOS and PMOS at 300K.

4. ANALYSIS

UNDER DIE-TO-DIE PARAMETER VARIATIONS

OF SUBTHRESHOLD LEAKAGE

Die-to-die variations include die-to-die channel length, tempera-

ture and voltage variations. For the purpose of yield estimation, ICs

are generally screened assuming a worst-case supply voltage.

Moreover, now-a-days, state-of-the-art voltage regulators are rela-

tively insensitive to the drawn current. Therefore, we can neglect

die-to-die voltage variations in our analysis. On the other hand, die-

to-die temperature variations are a function of total chip power and

correlate strongly to with-in-die process variations such as within-

die channel length variations. Therefore, we will calculate the total

chip power and die-temperature self-consistently as in [14] to study

the impact of die-to-die temperature variations. Die-to-die channel

length variations will be taken into account by varying the mean

value of channel length. To illustrate how die-to-die and within-die

variation impact subthreshold leakage distribution, we calculate

leakage distribution using both BSIM3.2 simulations and analytical

calculations for three cases. In case 1, we consider only the most

significant die-to-die process variation i.e., effective channel length

variation (3σ=5%). Equations (21a) and (21b) are used for calcu-

lating the leakage for BSIM and analytical calculations.

For

,

3

eff eff

L die to die Leff

L

µσ

− −

−≤≤

().(

Leak BSIM effnSUB n

IL W I

=

()

Leak Anaeff Leak Ana n

ILI

=

,

3

eff

)

)

eff

L die to die L

σ

− −

.

pSUB p

W I

I

+

µ+

,

1,,,

()

eff

L

eff

L

L

(

L

(

+

(21a)

,

,

1,1,,1,,

)

..

eff eff

LnLp

effeff

LL

eff eff

eff Leak Ana peff

LL

p

n

np

effeff

A

L

A

L

WeWe

ββ

ηη

−−

=+

(21b)

In the above equations ISUB,n and ISUB,p are subthreshold currents

calculated through BSIM. Equation (21b) is based on (13). In case

2, apart from die-to-die channel variations, we consider within-die

variations as well. Among within-die variations, we consider chan-

nel length and temperature variations only since they are most sig-

nificant (Figure 5.) We consider 10% within-die variations on top

of die-to-die variations. Equations (22a) and (22b) are used for

BSIM and analytical calculations.

=+

(

2,,1,,

1

eff

Leak Ana n Leak Ana nL

II

2,

() . (

n

) . (

p

⋅

)

Leak BSIMeffn eff

+

p eff

IL W I LW IL

(22a)

)

,

eff

within die L

2

,

n

S

β

−

=

2

2

,

2

within die L

−

2

within die T

−

,,

22

(.)

Ln

eff

T

eff

SS

ee

β

β

×

2,2,,2,,

()()()

Leak Ana

In the above equations, In and Ip are subthreshold currents calcu-

lated using BSIM assuming Gaussian distribution for channel

length and temperature. I2Leak,Ana,p , which represents analytically

estimated subthreshold current, is calculated in a similar way as

I2Leak,Ana,n. In case 3, we consider die-to-die temperature variations

apart from other variations considered in case 2. Die-to-die tem-

perature variations arise because of the couplings involved between

power dissipation and die temperature. These couplings are taken

into account by self-consistently evaluating the temperature as in

[14]:

()(

Totaleff Leak

PLI

TTP

θ

⇒+

Here I2Leak is calculated from (22a) or (22b). In the calculation,

we assume a microprocessor consisting of 96 million gates and

average total W/L per NMOS-PMOS pair was taken to be 15. We

use BPTM specified parameters in our analysis [17]. The results for

the above three cases at 300K are shown in Figure 6. The X-axis

plots the channel length variation (due to die-to-die channel length

variations) and Y axis plots the leakage power.

effLeak Ana n effLeak Ana peff

ILILIL

=+

(22b)

2

).

.

eff DD active

P

Total

LV

=+

(23)

Figure 6: Total subthreshold leakage power vs. mean die-channel

length at die temperature of 300K.

Total Leakage Power (W)

Figure 7: Total subthreshold leakage power vs. mean die-

channel length at die temperature of 320K

Figure 7 compares the three cases at a higher die temperature of

320K (47˚C). It can be observed that at an elevated die temperature,

leakage could be significantly larger than at 300K. Also, it can be

seen that within-die variations increase the leakage without increas-

ing the spread unlike die-to-die temperature variations. Further-

160

Page 6

more, chips with low average channel length will have high leakage

power, high temperature, and subsequently, even higher leakage

power because of temperature-power couplings.

5. YIELD ESTIMATION

We now estimate the distribution of total power across different

dies which can be used further to calculate the yield. The Gaussian

probability density function p(PTotal) can be calculated using:

(

efftotal

dL

⎝

Here, p(Leff) represents the p.d.f. for Leff and P(Leff) denotes the total

power at a mean effective channel length of Leff.

Figure 8 plots the probability density function for total leakage

power based on (24). As we take more variations into account, the

spread of the total leakage power distribution increases which im-

plies that larger number of dies have higher leakage power. Since

active power is relatively insensitive to variations and can be as-

sumed constant, the yield can be defined by the number of dies

having the leakage to active power ratio less than a maximum al-

lowable ratio (say r). Figure 9 plots the yield as a function of r for

three different cases.

()

)

()

()

total

P

eff

eff

eff

LP

L dP

LpPp

=

⎟⎟

⎠

⎞

⎜⎜

⎛

−=

−1

(24)

Figure 8: Leakage power probability density vs. ratio of leakage

power and active power at 320K.

Figure 9: Yield vs. ratio of leakage power and active power at 320K.

It can be clearly observed that variations always result in a lower

yield. In particular, die-to-die temperature variations due to electro-

thermal couplings between power and temperature significantly

lower the yield. For instance, if r is 35%, then yield is reduced

from 95% in case 1 to 91% in case 2 and to 72% in case 3. There-

fore, to get an accurate estimate of yield, within-die variations as

well as die-to-die variations should be taken into account.

6. CONCLUSION

A novel probabilistic approach to analyze the impact of within-

die and die-to-die process (P), temperature (T) and voltage varia-

tions (V) on subthreshold leakage has been presented which allows

an understanding of the relative sensitivities of subthreshold leak-

age to P-T-V variations. The results obtained are compared with

BSIM results and are found to be more accurate as compared to

those obtained from existing statistical models. Also, it has been

shown that die-to-die temperature variations significantly increase

the leakage due to the electrothermal couplings between subthresh-

old leakage power and temperature, especially at higher operating

temperatures. Furthermore, the leakage power distribution arising

due to within-die and die-to-die P-T-V variations has been calcu-

lated, which is subsequently used to estimate the leakage con-

strained yield under the impact of these variations. Also, it was

shown that ignoring within-die and die-to-die process and tempera-

ture variations can lead to significant errors in yield estimation,

which is further expected to degrade with technology scaling.

ACKNOWLEDGEMENTS

This work was supported by Intel Corp., Fujitsu Labs of America,

and the University of California-MICRO program. The authors

would also like to thank Dr. Vivek De and Dr. Frank O’Mahony of

Intel’s Circuit Research Lab for providing useful feedback.

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