Conference Paper

A Probabilistic Framework to Estimate Full-Chip Subthreshold Leakage Power Distribution Considering Within-Die and Die-to-Die P-T-V Variations

University of California, Santa Barbara, CA
DOI: 10.1109/LPE.2004.240888 Conference: Low Power Electronics and Design, 2004. ISLPED '04. Proceedings of the 2004 International Symposium on
Source: IEEE Xplore


This paper presents a probabilistic framework for full-chip estimation of subthreshold leakage power distribution considering both within-die and die-to-die variations in process (P), temperature (T) and supply voltage (V). The results obtained under this framework are compared to BSIM results and are found to be more accurate in comparison to those obtained from existing statistical models. Using this framework, a quantitative analysis of the relative sensitivities of subthreshold leakage to P-T-V variations has been presented. For the first time, the effects of die-to-die channel length and temperature variations on subthreshold leakage are studied in combination with all within-die variations. It has been shown that for accurate estimation of subthreshold leakage, it is important to consider die-to-die temperature variations which can significantly increase the leakage power due to electrothermal couplings between power and temperature. Furthermore, the full-chip leakage power distribution arising due to both within-die and die-to-die P-T-V is calculated, which is subsequently used to estimate the leakage constrained yield under the impact of these variations. The calculations show that the yield is significantly lowered under the impact of within-die and die-to-die process and temperature variations.

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    • "A full chip leakage estimation technique is presented to accurately account for power supply and temperature variations [4]. A probabilistic framework for full-chip subthreshold leakage power distribution considering within-die and die-to-die variations in process, temperature and supply voltage has been presented [5]. A full-chip subthreshold leakage power prediction model that takes into account within-die threshold voltage variation is presented and verified against statistical measurements in 0.18 µm CMOS [6]. "
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    ABSTRACT: This paper focuses on the impact of process variations on the estimation of static leakage power and its variability. A statistical methodology for the estimation of static leakage power dissipation due to subthreshold leakage and gate tunneling leakage in 65 nm CMOS digital circuits, in the presence of process variations, is presented. A 2-input NAND gate is used as a representa-tive library element, whose leakage power is extensively characterized, by rigorous mixed-mode simulations. Also, an analytical model for leakage power is proposed at the gate level in terms of the device resistance data, for computational simplicity. The proposed methodology is demonstrated by characterizing the variations in the leakage power of a 4-bit × 4-bit Wallace tree multiplier by an extensive Monte Carlo analysis. To extend this methodology to a generic technology library for process characterization, an optimal second order hybrid model is proposed by combining a piece-wise quadratic model obtained by Least Squares Method (LSM) and Response Surface Modeling (RSM) of leakage power of NAND gate directly in terms of process parameters, using Design of Experiment (DOE). We demonstrate that our hybrid models based statistical design approach can result in upto 95% improvement in accurate prediction of vari-ability with an error of less than 0.7%, with respect to worst case design. In terms of standard deviation, the predictability of leakage power distributions get tighter by atleast 13X, leading to considerable savings in the power budget of low power CMOS designs. This work aims to bridge the manufacturing to design gap, through the characterization of standard cell libraries for leakage power, in the presence of process variations.
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    • "For the purpose of yield optimization, distribution of design variables is modeled. Simulations results indicate that and variations can be modeled as normal distributions, which is a standard statistical model [32], [33]. But the normal distribution does not have a closed-form cumulative distribution function (cdf), which is necessary for the yield estimation. "
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    ABSTRACT: The supply voltage ( V <sub>dd</sub>) and threshold voltage ( V <sub>th</sub>) are two significant design variables that directly impact the performance and power consumption of circuits. The scaling of these voltages has become a popular option to satisfy performance and low power requirements. Subthreshold operation is a compelling approach for energy-constrained applications where processor speed is less important. However, subthreshold designs show dramatically increased sensitivity to process variations due to the exponential relationship of subthreshold drive current with V <sub>th</sub> variation and drastically growing leakage power. If there is uncertainty in the value of the threshold or supply voltage, the power advantages of this very low-voltage operation diminishes. This paper presents a statistical methodology for choosing the optimum V <sub>dd</sub> and V <sub>th</sub> under manufacturing uncertainties and different operating conditions to minimize energy for a given frequency in subthreshold operation while ensuring yield maximality. Unlike the traditional energy optimization, to find the optimal values for the voltages, we have considered the following factors to make the optimization technique more acceptable: the application-dependent design constraints, variations in the design variables due to manufacturing uncertainty, device sizing, activity factor of the circuit, and power reduction techniques. To maximize the yield, a two-level optimization is employed. First, the design metric is carefully chosen and deterministically optimized to the optimum point in the feasible region. At the second level, a tolerance box is moved over the design space to find the best location in order to maximize the yield. The feasible region, which is application dependent, is constrained by the minimum performance and the maximum ratio of leakage to total power in the V <sub>dd</sub> - V <sub>th</sub> plane. The center - - of the tolerance box provides the nominal design values for V <sub>dd</sub> and V <sub>th</sub> such that the design has a maximum immunity to the variations and maximizes the yield. The yield is estimated directly using the joint cumulative distribution function over the tolerance box requiring no numerical integration and saving considerable computational complexity for multidimensional problems. The optimal designs, verified by Monte Carlo and SPECTRE simulations, demonstrate significant increase in yield. By using this methodology, yield is found to be strongly dependent on the design metrics, circuit switching activity, transistor sizing, and the given constraints.
    IEEE Transactions on Semiconductor Manufacturing 03/2010; 23(1-23):77 - 86. DOI:10.1109/TSM.2009.2039184 · 1.00 Impact Factor
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    • "While, the authors separate the variations into global and local variations, the local variations are considered to be independent, and thus the effect of correlation is not factored into the final result; also, they do not provide an estimate of the standard deviation of full-chip leakage. Zhang et al. [8] in addition to considering process variations, also consider temperature and voltage variations. Instead of fitting the effect of process variations on leakage into an analytical equation, they use the BSIM model equations directly. "
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