Conference Paper

A Probabilistic Framework to Estimate Full-Chip Subthreshold Leakage Power Distribution Considering Within-Die and Die-to-Die P-T-V Variations

University of California, Santa Barbara, CA
DOI: 10.1109/LPE.2004.240888 Conference: Low Power Electronics and Design, 2004. ISLPED '04. Proceedings of the 2004 International Symposium on
Source: IEEE Xplore

ABSTRACT This paper presents a probabilistic framework for full-chip estimation of subthreshold leakage power distribution considering both within-die and die-to-die variations in process (P), temperature (T) and supply voltage (V). The results obtained under this framework are compared to BSIM results and are found to be more accurate in comparison to those obtained from existing statistical models. Using this framework, a quantitative analysis of the relative sensitivities of subthreshold leakage to P-T-V variations has been presented. For the first time, the effects of die-to-die channel length and temperature variations on subthreshold leakage are studied in combination with all within-die variations. It has been shown that for accurate estimation of subthreshold leakage, it is important to consider die-to-die temperature variations which can significantly increase the leakage power due to electrothermal couplings between power and temperature. Furthermore, the full-chip leakage power distribution arising due to both within-die and die-to-die P-T-V is calculated, which is subsequently used to estimate the leakage constrained yield under the impact of these variations. The calculations show that the yield is significantly lowered under the impact of within-die and die-to-die process and temperature variations.

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    ABSTRACT: This paper focuses on the impact of process variations on the estimation of static leakage power and its variability. A statistical methodology for the estimation of static leakage power dissipation due to subthreshold leakage and gate tunneling leakage in 65 nm CMOS digital circuits, in the presence of process variations, is presented. A 2-input NAND gate is used as a representa-tive library element, whose leakage power is extensively characterized, by rigorous mixed-mode simulations. Also, an analytical model for leakage power is proposed at the gate level in terms of the device resistance data, for computational simplicity. The proposed methodology is demonstrated by characterizing the variations in the leakage power of a 4-bit × 4-bit Wallace tree multiplier by an extensive Monte Carlo analysis. To extend this methodology to a generic technology library for process characterization, an optimal second order hybrid model is proposed by combining a piece-wise quadratic model obtained by Least Squares Method (LSM) and Response Surface Modeling (RSM) of leakage power of NAND gate directly in terms of process parameters, using Design of Experiment (DOE). We demonstrate that our hybrid models based statistical design approach can result in upto 95% improvement in accurate prediction of vari-ability with an error of less than 0.7%, with respect to worst case design. In terms of standard deviation, the predictability of leakage power distributions get tighter by atleast 13X, leading to considerable savings in the power budget of low power CMOS designs. This work aims to bridge the manufacturing to design gap, through the characterization of standard cell libraries for leakage power, in the presence of process variations.


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