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Dependence of thermal resistance on ambient and actual temperature
Abstract
We investigate the temperature dependence of thermal resistance. We extract the thermal resistance as a function of ambient temperature. The increase of thermal resistance due to self-heating leads to a non-linear relation between temperature and power dissipation. We show how to implement this in a compact model and what its effect is on simulations at high power dissipation.
... In simple terms, R TH00 represents the thermal resistance of the transistor if the thermal conductivities of all materials are equal to their k(T 0 ) value. The low-power thermal resistance R THB0 at an arbitrary T B in the range 250 to 450 K (nonlinear thermal effect due to the backside temperature) can be calculated as [22,26,47,53] ...
... where α (>0) is a dimensionless fitting parameter. The further thermal resistance growth due to the increase in P D (nonlinear self-heating effect) can be accounted for by invoking the Kirchhoff transformation as [5,22,26,47,53] ...
... It was found that in the absence of avalanche, assuming temperature-insensitive parasitic resistances, and neglecting the drop R B · I B T j − I B (T 0 ) , (16) holds. From (16), the V CB -and I E -constant V BE -T B curve can be modeled by (53), which inherently accounts for self-heating and the nonlinear thermal effect due to T B . By neglecting self-heating, (53) reduces to ...
This paper presents a critical and detailed overview of experimental techniques for the extraction of the thermal resistance of bipolar transistors from simple DC current/voltage measurements. More specifically, this study focuses on techniques based on a thermometer, i.e., the relation between the base-emitter voltage and the junction temperature. The theory behind the techniques is described with a unified and comprehensible nomenclature. Advantages, underlying approximations, and limitations of the methods are illustrated. The accuracy is assessed by emulating the DC measurements with PSPICE electrothermal simulations of a transistor model, applying the techniques to the simulated currents/voltages, and comparing the extracted thermal resistance data with the values obtained from the target formulation embedded in the transistor model. An InGaP/GaAs HBT and an Si/SiGe HBT for high-frequency applications are considered as case studies.
... where β > 0. Commonly accepted values for k(T 0 ), α, β corresponding to the most relevant semiconductors and metals are reported in Table 1. [22] and references therein 1.56 × 10 −4 [23] 1.25 [24] 1.3 [25], also reported in [26] 1.33 from elaboration of data in [20], and [27] from elaboration of data in [21] 1.4 [28] from elaboration of data in [23] 1.65 [22], although 1.3 seems better (see Ref. [2] in [29]) -GaAs 0.44 × 10 −4 [21] 0.37-0.46 × 10 −4 [22] and references therein 0.55 × 10 −4 [30] 1.25 [22] and references therein 1.27 [28] from elaboration of data in [30] -GaN 1.25-1.5 × 10 −4 [22] and references therein 0.43 [22] and references therein -InP 0.68 × 10 −4 [22] and references therein, [31] 0.696 × 10 −4 [32] 1.4 [22] and references therein 1.48 [31], also reported in [28] 4H-SiC 3.7 × 10 −4 [33,34] 1.29 [35] -6H-SiC 3.2-4.9 ...
... The R TH increase due to nonlinear thermal effects concurrently induced by T B and P D can be described as follows. Since for this ideal single-semiconductor device the thermal resistance is inversely proportional to the thermal conductivity [13,[17][18][19]28,29,39,45,46], then the R TH growth only due to T B > T 0 (for P D → 0 W, i.e., without the nonlinear self-heating effect) can be described by the power law [17,28,29,45] ...
... The R TH increase due to nonlinear thermal effects concurrently induced by T B and P D can be described as follows. Since for this ideal single-semiconductor device the thermal resistance is inversely proportional to the thermal conductivity [13,[17][18][19]28,29,39,45,46], then the R TH growth only due to T B > T 0 (for P D → 0 W, i.e., without the nonlinear self-heating effect) can be described by the power law [17,28,29,45] ...
This paper presents a comprehensive overview of nonlinear thermal effects in bipolar transistors under static conditions. The influence of these effects on the thermal resistance is theoretically explained and analytically modeled using the single-semiconductor assumption. A detailed review of experimental techniques to extract the thermal resistance as a function of backside temperature and/or dissipated power from DC measurements is provided; advantages, underlying approximations, and limitations of all methods are clarified, and guidelines for their correct application are given. Accurate FEM thermal simulations of an InGaP/GaAs and a Si/SiGe HBT are performed to verify the accuracy of the single-semiconductor theory. The thermal resistance formulations employed in the most popular compact bipolar transistor models for circuit simulators are investigated, and it is found that they do not properly describe nonlinear thermal effects. Alternative implementations of the more accurate single-semiconductor theory are then proposed for the future versions of the compact models.
... On the one hand, we have fabricated specific high-power resistors based on a highly doped epilayer with ns above 9.5×10 13 cm -2 , thus providing very high dissipated power, Pdiss, without applying too high bias, which somewhat simplifies the characterization tasks. On the other hand, we have used a self-consistent electrothermal Monte Carlo (MC) simulator to verify the lack of validity of commonly used (linear and non-linear) thermal resistance models at high levels of [6][7][8][9][10]. We finally propose a novel non-linear thermal resistance model which allows reproducing the experimental I-V curve of the resistors up to extremely high values of (above 150 W/mm). ...
... In order to account for the steeper increase of the device temperature at high levels of , in this second model the value of is not constant but follows the temperature dependence of the thermal conductivity . It is well know that thermal conductivity of semiconductors depends on the temperature according to, ( )~ [9,10], where and are characteristic parameters of each material [9]. As the thermal resistance is inversely proportional to the thermal conductivity, Paasschens et al. [10] proposed a temperature dependent thermal resistance, ( ), which will be used within this TRM-2: ...
... It is well know that thermal conductivity of semiconductors depends on the temperature according to, ( )~ [9,10], where and are characteristic parameters of each material [9]. As the thermal resistance is inversely proportional to the thermal conductivity, Paasschens et al. [10] proposed a temperature dependent thermal resistance, ( ), which will be used within this TRM-2: ...
We report on the modeling of self-heating in GaN-based devices. While a constant thermal resistance is able to account for the self-heating effects at low power, the decrease of the thermal conductance of semiconductors when the lattice temperature increases, makes necessary the use of temperature dependent thermal resistance models. Moreover, in order to correctly account for the steep increase of the thermal resistance of GaN devices at high temperature, where commonly used models fail, we propose a non-linear model which, included in an electro-thermal Monte Carlo simulator, is able to reproduce the strongly non-linear behavior of the thermal resistance observed in experiments at high DC power levels. The accuracy of the proposed non-linear thermal resistance model has been confirmed by means of the comparison with pulsed and DC measurements made in devices specifically fabricated on doped GaN, able to reach DC power levels above 150 W mm ⁻¹ at biases below 30 V.
... This can be ascribed to the decreasing l with the higher temperature. Z th is inversely proportional to l. Therefore Z th increases with T X [19][20][21]. For most materials used in power electronic packaging, l as function of temperature (T ) is given as follows in the relevant temperature range, that is, between −50°C and 200°C [19] ...
... Z th is inversely proportional to l. Therefore Z th increases with T X [19][20][21]. For most materials used in power electronic packaging, l as function of temperature (T ) is given as follows in the relevant temperature range, that is, between −50°C and 200°C [19] ...
... where l ref denotes l at the reference temperature T ref . The values of l ref and α of materials can be found in [19,20]. For silicon-based IGBT die, the l at 120°C is 102 W/m·K, which is 30.8% ...
The thermal characterisation of insulated gate bipolar transistor (IGBT) module is very important, since the production consistency and reliability are affected when IGBT is exploited in high temperature. To investigate the transient thermal behaviour of IGBT, a transient thermal impedance (Zth) measurement system was built using the electrical method with gate-emitter voltage as temperature-sensitive parameter. Factors affecting the Zth measurement, such as environment temperature, heating power, duty cycle and heating time, were discussed in detail. The Zth of each component within IGBT module was measured by selecting right heating time before thermal equilibrium. It is found that the Zth measurement has high accuracy and repeatability, which is helpful to understand how thermal performance of IGBT module varies with architecture and material properties for power electronic packaging.
... This can be ascribed to the decreasing l with the higher temperature. Z th is inversely proportional to l. Therefore Z th increases with T X [19][20][21]. For most materials used in power electronic packaging, l as function of temperature (T ) is given as follows in the relevant temperature range, that is, between −50°C and 200°C [19] ...
... Z th is inversely proportional to l. Therefore Z th increases with T X [19][20][21]. For most materials used in power electronic packaging, l as function of temperature (T ) is given as follows in the relevant temperature range, that is, between −50°C and 200°C [19] ...
... where l ref denotes l at the reference temperature T ref . The values of l ref and α of materials can be found in [19,20]. For silicon-based IGBT die, the l at 120°C is 102 W/m·K, which is 30.8% ...
Recently, silver paste, silver epoxy, and solders were commonly used as die-attach materials for power electronic packaging. Thermal performance of these materials should be paid attention to since reliability of sintered or soldered jointsis highly dependent on the thermal performance. To accurately investigate the transient thermal behavior of sintered or soldered joints in electronic applications, an improved way and system for thermal impedance measurement were developed in this paper. A series of measurements utilized gate-emitter voltage as temperature-sensitive parameter at varies heating time and heating power were conducted. Significantly, through changing the heat input, the specific thermal impedance of any layer could be obtained with high accuracy, repeatability, and stability. In this way, it would be useful to understand how thermal performance of power modules varies with architecture and materials for power electronic packaging.
... 1) Only in exceptional situations, in which the geometries and material parameters are over-simplified, the linear heat diffusion equations (36) and (37) can be solved in closed form. This difficulty is overcome by numerically solving (36) and (37) through a discretization method. ...
... 1) Only in exceptional situations, in which the geometries and material parameters are over-simplified, the linear heat diffusion equations (36) and (37) can be solved in closed form. This difficulty is overcome by numerically solving (36) and (37) through a discretization method. An efficient and accurate discretization method here used is FEM with second-order spatial approximation of the temperature rise m,α m (r, σ m ) over a tetrahedral mesh. ...
... Such a mesh, shown in Fig. 2, was rather cumbersome to generate due to the presence of layers with thickness much lower than horizontal dimensions and than thicknesses of other layers; it was created with smart selective refinement strategies-available in the recent software releases-and includes more than 1 million elements (tetrahedra). This COMSOL mesh is used for the second-order FEM discretization of the linear heat diffusion problems (36) and (37), by means of about 1.5 million DoFs. ...
A novel nonlinear model order reduction method is proposed for constructing one-port dynamic compact models of nonlinear heat diffusion problems for ultra-thin chip stacking technology. The method leads to models of small state-space dimensions, which allow accurately reconstructing the whole time evolution of the temperature field due to an arbitrary power waveform of practical interest. The approach is also efficient, since the computational time/memory requirements for constructing each dynamic compact model is about one order of magnitude lower than that corresponding to a single 3-D finite element method transient simulation of a nonlinear problem.
... Moreover, the Self-Heating (SH) increase due to the size reduction has drastically modified the transistor output characteristics. A large work about the improvement of the thermal response has been achieved and published in [24,25,26,27]. It has also allowed to model the thermal behavior in a 2D structure with an accurate extraction procedure. ...
... 26: Transit frequency f T as a function of the collector current for 0.2 × 5µm HS transistor, showing the different biases used for the ring oscillator. ...
The development of new BiCMOS technology will be possible, thanks to the SiGe:CHBTs technological improvements to reach dynamic performance beyond 0.5 THz. Animportant aspect to be investigated is the Safe Operating Area (SOA) beyond the traditionalBVCEO. In fact, due to the complexity of future architectures of HBTs (likethe B55X from STMicroelectronics) and their nanoscale size, an increase of the wear-outmechanisms occurring in these transistors is expected. In addition, because of the increasingdependence of circuit design on software tools, it is expected that additional effortswill be required to develop more predictive compact models. Thus, the SOA sub-projectis designed to describe the functional safety area of nanoscale SiGe:C HBTs allowing thecompact model to take into account critical aspects.After a short introduction, a precise description of the transistor operations beyondthe breakdown voltage is detailed in the second chapter. The compact model HICUM isimproved to account for the mechanisms occurring in this region to accurately model theavalanche regime and the pinch-in effect. This new model is validated on TCAD simulationsand through electrical measurements on different devices, architecture, geometriesand temperatures.In the third chapter, the investigation is deepen towards the device border’s operation.A study of the pinch-in effect and the snapback behavior is therefore realized to understandthe operation limitations at high currents and voltages and a stable operation regime isintroduced.In the fourth chapter, accelerated aging tests are carried out at the boundaries of thesafe operating area to submit the transistor to thermal and hot carriers stresses during itsoperation. An aging model is developed to account for the wear-out mechanism occurringin that regime.To conclude, this work allowed to increase the modeling of SiGe HBTs at high voltagesand currents accounting for the wear-out mechanisms occurring in that operation regime.
... It is understood that the higher driving current improves the performance of the LED by reducing the thermal resistance considerably (Zang et al. 2012). Based on the Debye-model, the increase in the driving current will affect the thermal resistance where the rise in driving current increases the thermal conductivity as the inverse proportionality between thermal resistance and conductivity shifts towards the lower resistance (Shanmugan and Devarajan 2014;Zinovchuk et al. 2008;Paasschens et al. 2004). ...
... High driving current causes the high injection of current density which induces the current crowding effect, the rate of heat generation in the LED increases thus rise the T j of the LED package (Zinovchuk et al. 2008). In addition, the increase in the temperature difference causes by the effect of temperature on changing the thermal conductivity of the thin films (Paasschens et al. 2004). Overall, it can be stated that the ZnO coated substrate perform well compared to the bare Al substrate. ...
ZnO thin films were deposited onto aluminium substrates at different substrate temperatures from 300 to 450 °C by chemical vapour deposition method using zinc acetate dihydrate as precursor. The effects of substrate temperatures on the thermal and optical performances of a light emitting diode package were investigated. The thermal transients show that thin film deposited at 400 °C has the lowest thermal resistance and junction temperature with a different difference of 1.3421 K/W and 2.7 °C respectively. The correlated colour temperature of the LED interfaced with ZnO prepared at 400 °C showed a good agreement with the thermal performance and exhibited the lowest correlated colour temperature as the driving current increases. The luminance shows that bare Al demonstrate the lowest luminosity compare to the coated thin film as TIM. The excess heat that trapped within the air gaps affects the heat flow. This eventually affects the luminosity of the LED. Furthermore, the AFM measurements of CVD 3 (400 °C) samples show low roughness values which contribute to good thermal resistance and junction temperature values. Overall, the present study shows that the performance of the LED has been enhanced with ZnO thin film used as TIM.
... Therefore, such nonlocal strategies can be invasive or/and unsuitable. One of the less invasive solutions is the use of accurate calorimeters [10]- [14], inspired on those employed for power converters efficiency evaluation [15]- [21]. Although their sensitivity and accuracy have been improved at cost of lengthening the acquisition time, they require slightly modifying the converter geometry without locally accessing to the die (die-level measurement). ...
... The thermal field is acquired on top of the die surface with an infrared (IR) thermographic system that makes possible thermal measurements at the die-level. Among all existing techniques for non-invasive thermal measurements [21] [22][27]- [33], IR thermography [34]- [36], combined with a lock-in detection strategy (IR Lock-In Thermography, IR-LIT) [31], has been selected because of its commercial availability, high thermal resolution (below 1 m°C) and high rejection to noise and thermal boundary conditions [37]- [43]. With this IR system, power losses and current distribution at the die-level can be carried out as follows. ...
test bench is proposed to study at die-level the power losses and current distribution in power devices. It is based on an infrared camera and a flexible half-bridge resonant inverter with a tunable resonance frequency
${\mathcal f}_\text{res}$
. With this set-up, the die surface temperature is acquired in steady state, while the device is under real operation. The power losses are derived from the temperature mean value averaged, first, over a few switching cycles and, after, across the die surface. By contrast, the current distribution is inferred from the spectral component of the surface thermal map at the switching frequency (
${\mathcal f}_\text{Sw}$
). As a proof of concept, two case studies are reported considering 650 V-40 A IGBTs soft- and hard-switched within and outside the Zero Voltage Switching (ZVS) condition. First, the power losses are analyzed under switching conditions representative of domestic induction heating applications (
${\mathcal f}_\text{res}$
= 29.6 kHz) at
${\mathcal f}_\text{Sw}$
= 40 kHz and
${\mathcal f}_\text{Sw}$
= 20 kHz. Second, the power losses and local current distribution are investigated when
${\mathcal f}_\text{res}$
= 9.25 kHz at
${\mathcal f}_\text{Sw}$
ranged from 8.91 to 9.51 kHz. Such results are assessed with power losses electrical measurements and simulations, obtaining a satisfactory agreement. Moreover, hot spots are identified as current crowding points at
${\mathcal f}_\text{Sw}$
, whose location is fixed by the bonding wires attachment to the die and the device edge termination. As main benefits of this technique, a higher spatial resolution is achieved and problems related with noisy electrical measurements resulting from the insertion of the used probes or transducers, power circuit stray elements or device packaging parasitics are avoided.
... In addition, g th is a weak function of temperature, which we have ignored. The effect of the temperature dependence of g th can be accounted for [6], although we are aware of no MOS transistor compact model that includes self-heating that does so. But the approach of [6] still models a device is being isothermal, which as discussed in the previous paragraph is an approximation, so does not account for the spatial dependence of temperature dependent quantities like mobility, intrinsic carrier concentration, etc. ...
... The effect of the temperature dependence of g th can be accounted for [6], although we are aware of no MOS transistor compact model that includes self-heating that does so. But the approach of [6] still models a device is being isothermal, which as discussed in the previous paragraph is an approximation, so does not account for the spatial dependence of temperature dependent quantities like mobility, intrinsic carrier concentration, etc. This is why we said previously that the self-heating correction procedure of Fig. 3 [2] "appears" to be straightforward; the process is straightforward, but it is not exact because it ignores the nonuniformity of temperature in a device and the temperature dependence of g th 2 . ...
... Note that the P D and T B related partial derivatives of 636 the R th (P D , T B ) relation need to be neglected in order to 637 obtain (22), (24), and (25). Up to this point, the Early effect 638 is taken into account. ...
Many different methods have been proposed in the literature for the extraction of the thermal resistance of heterojunction bipolar transistors (HBTs). This review presents a detailed evaluation and discussion of several widely used methods. Special emphasis is put on a generalized analysis of the underlying assumptions, suitable operating point range, and necessary measurement effort of each method. The accuracy of each method is determined by applying it to data based on circuit simulations of advanced SiGe and III-V HBT technologies. Experimental data from those technologies are used to highlight practical issues. A guideline for the selection of the most suitable method in practice is also given.
... This is directly related to thermal impedance. In particular, this is useful as thermal impedance is temperature dependant [12], and as section temperature remains constant during continuous athermalisation, this gives thermal impedance for a given temperature, however it should be noted that this variance was not measured in this study. The following subsections will consider the structural features of the devices under study. ...
Thermal impedance is an important material property which can be used in the design, optimisation and operation of semiconductor lasers. In this study, a new method is proposed for measurement of thermal impedance for all-active semiconductor lasers, using the athermalisation condition. This method is capable of measuring thermal impedance of several device sections at the same time for simple devices, while being capable of measuring the thermal impedance of the device as a whole for more complex structures. Three DBR devices of the same material properties were evaluated and the average impedance length product (Z th L) was determined to be 29.3±2.1 o C μm/mW and 39.33±2.8 o C μm/mW for the gain and grating sections respectively. Additionally, thermal impedance length product of the entire widely tunable Vernier device based on the same material was also determined to be 31.3±0.5 o C μm/mW.
... In last decades, off-chip methods have appeared to thermally characterize integrated circuits (ICs) at die level [20]. They perform spatially-resolved measurements of temperature dependent parameters; e.g., resistance [21], refractive index [22], or thermal radiation [23], [24], [25], [26]; and show a great potential for MMIC thermal analysis. However, with off-chip measurements in the time domain, the thermal interaction among all MMIC parts cannot always be avoided, and determining the local power consumption per component is not feasible. ...
The thermal resistance of a High Electron Mobility Transistor (HEMT) forming part of a Monolithic Microwave Integrated Circuit (MMIC) is non-invasively extracted under real working conditions (electrical and thermal) by infrared thermal imaging. The HEMT thermal resistance considers the device local maximum temperature and dissipated power. An experimental approach to this end is currently not available, as the HEMTs thermal interaction does not allow extracting its individual heat generation. Thanks to thermal field confinement offered by heat source frequency modulation, the power dissipation in each device is inferred, making feasible its individual thermal resistance extraction. As a result, reasonable values of the local thermal resistance of each individual HEMT integrated in the MMIC (i.e., 57.8+3.4 C/W and 24.8+1.4 C/W) are obtained in agreement with studies on discrete devices available in the literature.
... The process is the same as that present in Fig. 2(a). If the R th is temperature dependent [10], an equation similar to Eq. (4) or (6) is obtained with Taylor expansion around T i-1 . ...
Different approaches to implement self-heating effects in a compact model are evaluated. The traditional approach using a sub-circuit with the addition of an internal node can lead to significant increase in the simulation time. In contrast, by directly solving self-heating equations, the internal node is eliminated in the circuit Jacobian matrix. The resulting simulation time can be shortened in principle up to 60% or more without sacrificing the accuracy. The accuracy and time for self-heating simulations formulated using different approaches are compared in this work to study their tradeoff. In addition, a generic approach to eliminate the need for internal nodes is proposed and demonstrated using the non-quasi-static effect model.
... Because there must be a temperature gradient in a device when self-heating occurs, for the generated power to be able to flow out of the device, the effective thermal resistance R th,eff cannot simply be calculated as R th at the sum of the ambient temperature T a and the local temperature rise T from self-heating. In JFETIDG, this is handled using the technique described in [29] R th,eff = ...
This paper presents the details of JFETIDG, a compact model for independent dual-gate junction field-effect transistors with any combination of p-n junction or MOS gates. JFETIDG accounts for nonlinearity from depletion pinching, velocity saturation, and self-heating, and includes extensive modeling of geometry and temperature dependences, parasitics, noise, and statistical variations. We also demonstrate that it accurately models long channel junctionless MOS transistors. The model is verified by comparison with TCAD simulations and experimental data. Verilog-A code for JFETIDG is available in the public domain.
... Table 3 shows that replacing the thermally-resistive ternary InGaAs emitter cap layers with GaAs (without altering the cap thickness) yields a − 0.7% R TH reduction (but the emitter resistance may significantly grow up); similarly, adopting an Al 0.25 Ga 0.75 As layer for the deep Table 2 Thermal conductivity parameters used for FEM simulations. Material Thermal conductivity k(T 0 ) [W/μm K] Temperature dependence GaAs 0.46 × 10 −4 [40] Eq. (1), m = 1.25 [40,43,44] In 0.5 Ga 0.5 As 0.048 × 10 −4 [40] Eq. (1), m = 1.175 [40] In x Ga 1 − x As 0.092 × 10 −4 [40] average in the layer Eq. (1), m = 1.212 [40] In 0.49 Ga 0.51 P 0.052 × 10 −4 [40] Eq. (1), m = 1.4 [40] Al 0.25 Ga 0.75 As 0.131 × 10 −4 [40] Eq. (1), m = 1.28 [40] (not used in this work) Ion-implanted GaAs 0.0046 × 10 −4 Eq. (1), m = 1 ...
This paper presents an extensive numerical analysis of the thermal behavior of InGaP/GaAs HBTs for handset applications in a laminate (package) environment. Both wire-bonding and flip-chip technologies are examined. The combination between an accurate, yet fast, simulation capability and the Design of Experiments technique is employed to quantify the impact of all the key technology parameters and explore a wide range of operating conditions.
... sinks aids in reducing the junction temperature of LEDs. Paasschens et al [14] explored the dependence of thermal resistance on ambient and actual temperature. They proposed a method to implement a non-linear relation between temperature and power dissipation into a compact model simulation. ...
Natural convection air cooling becomes the natural choice for low-cost electronic products. Innovative design of heat sinks and choice of material for heat sinks are adoptions for good thermal management solutions. In this study, Light Emitting Diodes (LEDs) were mounted on 4 different designs (HS 1 , HS 2 , HS 3 , HS 4) of heat sinks and junction temperature (T j) and thermal resistance (R th) were compared with plain rectangular heat sink (HS plain). Computational fluid dynamic (CFD) models were generated by FloEFD 15 software to numerically evaluate performance of LEDs mounted on the designed heat sinks. Experimental validations were done using Thermal Transient Tester (T3ster). The results demonstrate good adherence of simulated predictions and experimental values and maximum deviation of 4.68% was reported. The thermal performance was studied by evaluating thermal resistance of heat sink package using cumulative structure functions. The influence of input power of heat source and ambient temperature were also presented. At 25ºC ambient temperature, R th and T j of HS 1 was found to be 60% and 45% lower than HS plain. For increase in ambient temperature from 25 ºC to 80 ºC, HS 1 was upholding higher thermal performance due to persistent reflow contours at solid-fluid interface. This study emphasizes the need for effective design approach to achieve lower thermal resistance of electronic packages.
... 10. Generally thermal capacitance is inversely proportional to thermal resistance [73]. ...
The scope of this review paper is to consolidate various thermal factors which affect the performance of high power LEDs and also to summarize various cooling methods which improve both the efficiency and lifetime of LED lamps. Thermal factors such as thermal resistance, thermal spreading resistance, thermal interface material, thermal capacitance, active and passive cooling systems suitable for high power LED packages are discussed. The effect of junction temperature on the colour of emitted light and life of LED is also explored. Junction temperature of the LED depends on the current supplied and type of cooling system used. Higher junction temperature with poor cooling leads to shift in the light colour and drastically reduces the LED life. From the review it was found that heat sink and heat pipes are best solution for heat dissipation and in some applications active cooling systems using electric fan provided best results for LED lamps. © 2016 Eastern Macedonia and Thrace Institute of Technology. All rights reserved.
... The correlation of thermal resistance and ambient temperature has been studied for several power semiconductor devices [9]- [12]. The presented studies in [9] and [10] on Light Emitting Diodes (LEDs) and the low power transistors may not be applicable to the high power IGBTs due to the differences in materials and geometries. In [11], the dependence of IGBT thermal resistance on the power loss is experimentally studied, whereas it is difficult to apply the results in circuit simulations due to a lack of quantitative conclusions. ...
A basic challenge in the IGBT transient simulation study is to obtain the realistic junction temperature, which demands not only accurate electrical simulations but also precise thermal impedance. This paper proposed a transient thermal model for IGBT junction temperature simulations during short circuits or overloads. The updated Cauer thermal model with varying thermal parameters is obtained by means of FEM thermal simulations with temperature-dependent physical parameters. The proposed method is applied to a case study of a 1700 V/1000 A IGBT module. Furthermore, a testing setup is built up to validate the simulation results, which is composed of a IGBT baseplate temperature control unit, an infrared camera with a maximum of 3 kHz sampling frequency, and a black-painted open IGBT module.
... The variation in the temperature across the studied locations is shown in Figure 12. The thermal resistivity measured in the laboratory with weak positive correlation (R= 0.44) agrees with observation of IEEE (1998), and Paasschens et al (2004) but the field measurements with negative correlation (R= -0.03) differ from this. The drop in thermal conductivity of tar sand in the studied locations with respect to increase in temperature (Figure 12a and b) was in agreement with the observation of Somerton (1973) on tar sand and Dubow et al (1978) on oil shale. ...
In bitumen recovery from tar sand where heat transfer takes place through injection of thermal energy into the tar sand formation, it is of great importance to estimate the thermal properties of such tar sand. The aims of this research is to determine the thermal properties of tar sand in the Eastern Dahomey basin, Nigeria with a view to having more information in planning for thermal recovery of the tar sand.
Twelve locations were established along the tar sand belt in order to measure its thermal properties. The thermal properties of the tar sand were measured in-situ using KD2 Pro thermal analyzer. In laboratory, thermal properties of samples from each location were measured and their physical properties that influenced them (such as grain size distribution, percentage by weight of bitumen content, moisture content, bulk density, porosity and dry density of the samples) were determined. Thermal conductivity, specific heat and bulk density were used to calculate the thermal effusivity of the tar sands.
Positive correlations were observed between the values of the field and laboratory measurements of thermal
resistivity, thermal conductivity, thermal diffusivity, thermal effusivity and volumetric specific heat with R-values
0.86, 0.85, 0.81, 0.78 and 0.49 respectively. It was observed that the thermal properties of the tar sand determined have close similarities with those reported on Athabasca tar sand of Canada. This implies that the thermal recovery process used in the Athabasca basin could also be employed in the Eastern Dahomey basin, Nigeria.
... So, selfheating becomes a major concern. In fact, the base-emitter junction temperature has a great impact to the device electrical performance [1,2,5]. Modelling this phenomenon for accurate circuit design needs a good description of the thermal impedance. ...
... So, selfheating becomes a major concern. In fact, the base-emitter junction temperature has a great impact to the device electrical performance [1,2,5]. Modelling this phenomenon for accurate circuit design needs a good description of the thermal impedance. ...
The present work investigates the impact of transistor layout on both the RF and thermal performance of 90-nm SiGe heterojunction bipolar transistors (HBTs). The resulting performance shows only slight degradation in small-signal RF figures-of-merit, while large-signal RF figures-of-merit relevant to power amplifiers (PAs) are improved. Thermal resistance and capacitance were extracted for five different SiGe HBT layouts with the same total emitter area. Additionally, a favorable trade-off exists between RF performance figures-of-merit and thermal parameters; namely, the thermal time constant can be reduced by up to 37% with optimal layout, with only slight degradation (up to 8%) in RF performance. These optimal device layout variations can help circuit designers mitigate thermal memory effects at the device level, thereby improving the overall large-signal linearity of PAs.
In this article, we present and evaluate compact static thermal model parameter extraction techniques for modern silicon germanium heterojunction bipolar transistors (SiGe HBTs). We found that the model implementation of thermal resistance (
${R}_{\text {th}}$
) based on only junction temperature is implicit requiring time-consuming iterative procedure which may lead to potential instabilities. Dedicated extraction techniques are proposed for obtaining compact model-specific
${R}_{\text {th}}$
and its temperature coefficient. The proposed method is primarily validated on SPICE generated synthetic data. Next in order to showcase a compact model-independent verification, we also test the method using detailed thermal simulation from TCAD. Finally, we apply our extraction technique on measured data from fabricated transistors. The results are benchmarked to already obtained nominal
${R}_{\text {th}}$
values from the same device family.
An extensive evaluation of different techniques for transient and dynamic electro-thermal behavior of microwave SiGe:C BiCMOS hetero-junction bipolar transistors (HBT) and nano-scale metal-oxide-semiconductor field-effect transistors (MOSFETs) have been presented. In particular, new and simple approach to accurately characterize the transient self-heating effect, based on pulse measurements, is demonstrated. The methodology is verified by static measurements at different ambient temperatures, s-parameter measurements at low frequency region and transient thermal simulations. Three dimensional thermal TCAD simulations are performed on different geometries of the submicron SiGe:C BiCMOS HBTs with fT and fmax of 230 GHz and 290 GHz, respectively. A comprehensive evaluation of device self-heating in time and frequency domain has been investigated. A generalized expression for the frequency-domain thermal impedance has been formulated and that is used to extract device thermal impedance below thermal cut-off frequency. The thermal parameters are extracted through transistor compact model simulations connecting electro-thermal network at temperature node. Theoretical works for thermal impedance modeling using different networks, developed until date, have been verified with our experimental results. We report for the first time the experimental verification of the distributed electrothermal model for thermal impedance using a nodal and recursive network. It has been shown that, the conventional single pole thermal network is not sufficient to accurately model the transient thermal spreading behavior and therefore a recursive network needs to be used. Recursive network is verified with device simulations as well as measurements and found to be in excellent agreement. Therefore, finally a scalable electro-thermal model using this recursive network is developed. The scalability has been verified through numerical simulations as well as by low frequency measurements and excellent conformity has been found in for various device geometries
Purpose
The paper aims to study the influence of the Cu-Al2O3 films coated Cu substrate as thermal interface material on the thermal and optical behaviour of the LEDs package and the annealing effect on the thermal and optical properties of the films.
Design/methodology/approach
Layer stacking technique is used to deposit the Cu-Al2O3 films through magnetron sputtering and annealing process were conducted on the synthesized films.
Findings
In this paper, it is found that un-annealed Cu-Al2O3 coated Cu substrate exhibited low value of thermal resistance compared to the bare Cu substrate and previous work. Also the annealing effect does not have significant impact on the changes of properties of the films.
Research limitations/implications
It is deduced that the increase of Cu layer thickness can further improved the thermal properties of the deposited film, which can reduced the thermal resistance of the package in system level analysis.
Practical implications
The paper suggested that the Cu-Al2O3 coated Cu substrate can be used as alternative thermal interface material for the thermal management of LEDs application.
Originality/value
In this paper, Cu substrate is used as the substrate for the Cu-Al2O3 films as Cu has higher thermal conductivity compared to the Al substrate in previous work.
In this work, Lock-in Infrared Thermography (LIT) is presented as a powerful tool for failure analysis in power devices. These devices are electrically characterized in the frequency domain by thermal means to activate weak spots responsible for their misbehavior. As case studies, two different power devices are inspected using the LIT technique: a Vertical Double Diffused MOS (VDMOS) presenting an elevated gate leakage current and a SiC Schottky Barrier Diode with Tungsten contact (W-SBD) presenting a Schottky barrier modification by metal contact change.
This paper discusses challenges and opportunities for thermal management of information and communications technologies equipment, with a particular focus on telecommunications equipment. This paper identifies the key drivers for network traffic growth and how these increasing traffic demands are driving innovations in telecommunications, requiring the development of new and novel thermal management technologies to meet the product performance and reliability requirements. Application areas discussed include photonics, wireless networking, extreme heat density applications, and liquid cooling, with spatial scales ranging from individual transistors up to data center and telecom central offices. A perspective on the anticipated technology trends, key technical challenges, and opportunities for innovation and impact is also presented.
The existing industry standard compact models, VBIC and HICUM, are used to model devices using a linear thermal resistance network. However, the thermal resistance of the SiGe Heterojunction Bipolar Transistor (HBT) depends on the amount of power dissipated in the device. The increase of thermal resistance caused by self-heating due to the unsymmetrical emitter geometry and deep trenches lead to a non-linear relation between temperature and power dissipation. In this paper, a current controlled voltage source (CCVS) is used to account for the variation in current to model the thermal resistance of the device.
This paper investigates alternative topologies of silicon germanium heterojunction bipolar transistors designed and fabricated in the state-of-the-art BiCMOS process from STMicroelectronics for improved safe-operating characteristics. Electrical and thermal behaviors of various structures are analyzed and compared, along with a detailed discussion on drawbacks and advantages. The test structures under study are different in terms of emitter-finger layouts as well as the metal stacks in the back-end-of-line. It is observed that the multifinger transistor structures having nonuniform finger lengths with wider area enclosed by the deep trench and higher metallization stacks yield an improved thermal behavior. Therefore, the safe-operating area of multifinger transistors can be extended without degrading the RF performances.
A computationally efficient model for static self-heating and thermal coupling in a multi-finger bipolar transistor is proposed. Compared to an existing state-of-the-art model, our model differs only in the implementation strategy keeping the physical basis intact. The formulated model is implemented in Verilog-A without using any voltage controlled voltage sources. Temperature dependence of the thermal resistances are considered within the framework of the model. The number of extra nodes in our model reduces to 2n from n 2 required in the state-of-the-art model with n as the number of emitter fingers in a transistor. The simulation results of our model are found to be identical with those of the state-of-the-art model demonstrating the capability of accurately considering the static self-heating and thermal coupling in a simple way. The model is found to accurately predict the measured data of a five-finger transistor. It is found that in high current operating regimes, our five finger transistor model simulates around 11% faster compared with the state-of-the-art model.
The effect of void on characteristics of the laterally diffused metal oxide semiconductor (LDMOS) power amplifier (PA) is analyzed using the thermal and circuit analysis together. Thermal analysis is performed for finding the junction temperature of LDMOS PA as void area changes. Circuit analysis is performed from these results and LDMOS PA libraries. The analysis results show the linearity, gain, and efficiency degradation in the LDMOS PA as a result of the increase in void area. And this simulation methodology can be used for the design of the PA. (c) 2016 Wiley Periodicals, Inc.
This paper presents a compact model for an integrated 3-terminal PIN diode suitable for SPICE simulation. The model described within represents a significant extension to the standard 2-terminal diode model of SPICE, capturing phenomena critical to the accurate prediction of diode behavior in modern integrated process technologies. In particular, the inclusion of self-consistent electrothermal modeling and substrate injection effects is key to improving simulation accuracy for diodes operating in a forward conductive state, such as would be common for PIN diodes. The model is implemented in Verilog-A and hardware-verified results are presented for a 90nm SiGe BiCMOS technology featuring a high-performance integrated PIN diode.
Thermal impedance of IGBT modules may vary with operating conditions due to that the thermal conductivity and heat capacity of materials are temperature dependent. This paper proposes a Cauer thermal model for a 1700 V/1000 A IGBT module with temperature-dependent thermal resistances and thermal capacitances. The temperature effect is investigated by Finite Element Method (FEM) simulation based on the geometry and material information of the IGBT module. The developed model is ready for circuit-level simulation to achieve an improved accuracy of the estimation on IGBT junction temperature and its relevant reliability aspect performance. A test bench is built up with an ultra-fast infrared (IR) camera to validate the proposed thermal impedance model.
We present the Mextram model, an industrial world standard compact model for bipolar transistors, showing the identity, philosophy and capabilities of the model. Mextram has been developed to capture all terminal characteristics of bipolar transistors that are relevant to industrial electronic circuit design of any Si or SiGe bipolar transistor, under all relevant practical circumstances. History, basic structure and features of the model are discussed, including simulation of heating effects, noise, geometrical scaling and statistical analysis. The relevance of the refined topology of its equivalent circuit, to simulation of advanced ac-characteristics of modern high-speed Si and SiGe transistors is extensively demonstrated.
Effects of the back-end-of-line layers up to metal-1 on the self-heating and thermal coupling in a multi-finger silicon germanium heterojunction bipolar transistor (SiGe MFT) are investigated. It is observed that the rise in junction temperature is overestimated if the BEOL effects are not considered. A new method for estimating the thermal coupling coefficients is proposed emulating the real operating condition. The proposed methodology demonstrates that the thermal coupling is increased in real operating condition and the estimated coupling coefficients are almost independent of the dissipated power. Further an empirical closed-form formulation is proposed for estimating the coupling coefficients analytically and for subsequently using in compact model simulation. The formulation is found to predict the coefficients quite accurately. Compact model simulations using the analytically obtained coupling coefficients show excellent model agreement with the static and dynamic 3D TCAD simulation data for junction temperature. Finally the model is validated against the measured data corresponding to an SiGe MFT fabricated using B55 technology from ST microelectronics.
In many new applications like communication and automotive electronics the usage of integrated high voltage MOS transistors (LDMOS and DMOS) requires highly accurate compact models. In this chapter we present a deep look into special LDMOS transistor behavior and discuss state of the art sub-circuit modeling with BSIM/EKV core and JFET/Resistor approach. Parasitic diode and bipolar effects are discussed and modeling suggestions are presented. The EKV high voltage model developed by Swiss Federal Institute of Technology (EPFL) and the MM20 high voltage model introduced by NXP Research (formerly Philips Research) Laboratories is demonstrated in detail. The first CMC (Compact Modeling Council) standard high voltage MOSFET model HiSIM_HV developed by Hiroshima University is explained as well. Finally, characterization and measurement strategies for LDMOS modeling are described.
A strategy for compact modeling the static thermal coupling between the emitter fingers of SiGe heterojunction bipolar transistors (SiGe-HBTs) is described. An extraction methodology that includes the nonlinear temperature dependence of the thermal conductivity is introduced and applied to suitable test structures. The experimental results are used for calibrating a 3-D numerical solution of the equation for heat conduction based on a Green's function approach. The latter can then be employed for generating thermal coupling networks for arbitrary transistor configurations.
In this brief, we demonstrate a straightforward approach to obtain isothermal electrical characteristics of state-of-the-art SiGe:C BiCMOS heterojunction bipolar transistors designed for mmWave applications. DC and conventional continuous-wave RF measurements are performed at different chuck temperatures (Tchuck). Knowing the thermal resistance (RTH) of the device, all the isothermal dc and ac (above thermal cutoff frequency) data can be determined. The validation of the methodology is demonstrated by comparing the results with the pulsed dc and pulsed RF measurements, which are found to be in good agreements. This method could be applied with a standard measurement equipment.
The main reliability issue in SiGe heterojunction bipolar transistors (HBT) is the cumulative base current degradation which they may experience during circuit operation. This continuous transistor ageing is the result of the interplay between oxide interface trap creation and annihilation. Based upon long-term mixed-mode (up to 1000 h) and reverse (up to 100 h) stress tests this study discusses in detail the change of ageing rate over time and how this impacts the dependence on stress-voltages and stress-currents. Additionally, investigation of degradation as function of ambient temperature under both stress types reveals stress specific thermal behavior. These results are put together into an ageing function useful for integration into compact models and effectively replacing “life-time” definitions.
At high enough junction temperatures degradation can be reversed, leading to an efficient thermal recovery of the HBTs within one hour independent of previous transistor degradation. Finally, with a simple stress test imitating the switching between mixed-mode ageing and thermal recovering states in HBT duty cycles, it could be demonstrated that DC mixed-mode stress used for standard reliability characterization represents an upper limit for degradation of SiGe HBTs in RF circuits.
Analytical expressions for the electrothermal parameters governing thermal instability in bipolar transistors, i.e., thermal resistance RTH, critical temperature Tcrit and critical current JC,crit, are established and verified by measurements on silicon-on-glass bipolar NPNs. A minimum junction temperature increase above ambient due to selfheating that can cause thermal breakdown is identified and verified to be as low as 10-20°C. The influence of internal and external series resistances and the thermal resistance explicitly included in the expressions for Tcrit and JC,crit becomes clear. The use of the derived expressions for determining the safe operating area of a device and for extracting the thermal resistance is demonstrated.
We demonstrate the results of two-dimensional (2-D) hydrodynamic simulations of one-finger power heterojunction bipolar transistors (HBTs) on GaAs. An overview of the physical models used and comparisons
with experimental data are given. We present models for the thermal conductivity and the specific heat applicable to all relevant diamond and zinc-blende structure semiconductors. They are expressed as functions of the lattice temperature and in the case of semiconductor alloys, of the material composition.
Keeping device operating temperatures within reasonable limits is
necessary for reliability of all ICs and important for achieving the
expected performance for many ICs. GaAs heterojunction bipolar
transistors (HBTs) offer high speed and good device matching
characteristics that are attractive for many high-speed circuits, but
they are more susceptible than other IC technologies to the unexpected
generation of very high junction temperatures. The reasons for this
tendency are discussed, and an HBT sample-and-hold (S/H) circuit that
had device temperature rises of over 300°C is described. To address
this problem, a new thermal simulation tool called ThCalc was created.
ThCalc calculates the temperature profile of an IC and runs fast enough
to allow calculations on a whole chip. ThCalc was used to redesign the
S/H IC to reduce the largest temperature rise by a factor of 2.7 with a
minimal impact on circuit size
A general model for the dependence of integrated device thermal resistance on substrate backside temperature and power dissipation for Si, InP and GaAs substrates is derived by consideration of the role of temperature dependent thermal conductivity in each of these effects. Linearization of these model components is carried out to extract computationally simple expressions that retain very close agreement to the full equations. A parameter extraction and scaling procedure is developed which allows the linearized models to be used in a practical modeling environment. The performance of extracted and scaled model parameters in predicting thermal resistance is compared to measurements for InP substrate devices, and the agreement and predictions are found to be within 5% of measurements for two geometries, for power levels to 3 mW/μm2 and over a 165 °C substrate temperature range. The InP device model is also implemented as a subcircuit in hspice using behavioral sources, and the results confirmed with circuit simulation.
Kirchhoff's transformation is summarised in a form appropriate for semiconductor-device heat sinks and then illustrated with a brief application to the thermal resistance of a GaAs laser. Under the most common semiconductor boundary conditions his transformation immediately converts the steady-state linear temperature rise (based on a temperature-independent conductivity σ0) of a uniform heat sink of any shape into the nonlinear rise [based on a temperature-dependent conductivity σ(T) of any functional form].
A method is presented for extracting the temperature dependences
of bipolar transistor terminal currents, while cancelling effects of
self-heating. The method allows extraction at high currents where simple
models fail. Results can also be used to extract thermal impedance to
model self-heating in suitably modified circuit simulators
A revision is presented of the technique to determine the junction temperature and thermal resistance of bipolar transistors. It is based on the temperature sensitivity of the base-emitter voltage when biasing the device under constant emitter current. It accounts correctly for the self-heating of the device during the measurement. Results are obtained for devices fabricated on silicon-on-insulator (SOI) and bulk silicon having different emitter widths and lengths. An increment of the thermal resistance is found for SOI devices with respect to bulk.
A rigorous mathematical treatment of dynamic self-heating in
semiconductor devices is presented. Two formulations for the admittance
parameters are given. The thermal behavior of the device is referred to
device temperature in the first formulation, and to ambient temperature
in the second. Contrary to previous work, nonlinear thermal effects are
included. An analytical model for the thermal resistance is derived
which confirms the relevance of these effects. Applications of the above
results to device modeling and thermal characterization are studied in
detail by means of numerical simulations. Possible sources of
inaccuracies are evidenced. Finally, it is shown that the differential
analysis of thermal feedback provides a general and rigorous means to
determine the conditions for the onset of thermally-induced
instabilities
A new technique is presented that can directly extract the mean
device junction temperature of heterojunction bipolar transistors (HBTs)
under high self-heating operating conditions. The method uses three
trivial DC measurements of the device where the junction temperature is
known to be the same. This paper details the technique and applies it to
both closely and widely spaced multi-finger HBT's, and compares the
results to methods already known
A novel electrical method to accurately measure the thermal
resistance of heterojunction bipolar transistors (HBT's) is presented.
The key advantage of the method is its simplicity, because it requires
only the measurement of the device DC output characteristics at two
different temperatures. In this brief, the measurement technique is
illustrated, applied to multifinger HBT's and compared with other
methods
An electrical method to determine the junction temperature of a
power bipolar transistor is presented. The success of this method does
not rely on the constancy of thermal resistance over the wide range of
operating temperatures. It is hence suitable for transistors operating
at high power densities where conventional measurement techniques would
not apply. Using this method, we establish that the junction temperature
can be 40°C higher than the product of the low temperature thermal
resistance and the power dissipation
A method of measuring the junction temperature and associated
thermal resistance of heterojunction bipolar transistors by using the
temperature dependence of the DC gain is described
Topical Meeting on Silicon Monolithic Integrated Circuits in RF systems
- J.-S. Rieh Proc