Experimental comparison of substrate structures for inductors and transformers
ABSTRACT An experimental comparison of the substrate structures for silicon inductive devices is proposed. On-wafer measurements for both inductors and stacked transformers revealed that better performance is achieved by exploiting a n+-doped buried layer as a patterned ground shield. The proposed solution increases inductor quality factor and allows a wide operative bandwidth for transformers to be achieved, as well. Moreover, owing to a well-defined RF ground reference, cross-talk phenomena are inherently reduced. Finally, the buried layer patterned ground shield highly simplifies substrate modeling and allows accurate electromagnetic simulations to be easily carried out.
Conference Proceeding: A scalable model for silicon spiral inductors[show abstract] [hide abstract]
ABSTRACT: A simple model for monolithic spiral inductors on silicon substrates is presented. Each lumped element of the model is related to the layout geometry by analytical equations. Moreover, a novel equation for series resistance is also proposed. The model was validated by comparisons with on-wafer measurements over a wide range of geometrical layout parameters.Microwave Symposium Digest, 2003 IEEE MTT-S International; 07/2003
Conference Proceeding: A 5-GHz monolithic silicon bipolar down-converter with a 3.2-dB noise figure[show abstract] [hide abstract]
ABSTRACT: A monolithic 5-GHz down-converter consisting of a low noise amplifier (LNA) and a double-balanced mixer was designed using a 46-GHz-f<sub>T</sub> silicon bipolar process. The down-converter exhibits a SSB noise figure as low as 3.2 dB, a 24-dB power gain, and an input compression point of -23 dBm. It was assembled in a 4 × 4 mm = low-cost QFN 16-lead plastic package and draws only 18 mA from a 3-V power supply.Radio Frequency Integrated Circuits (RFIC) Symposium, 2003 IEEE; 07/2003
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ABSTRACT: The noise figure in low-noise radio frequency cascode amplifiers using narrow-band input-impedance matching is exhaustively analyzed and accurate equations are derived which fit simulated results well. Moreover, the effect on noise performance of different impedance-matching approaches is discussed and fundamental limitations caused by specific matching networks are pointed out. Finally, an improved matching network is proposed which reduces dominant noise components, greatly improving noise figure. By using the same process parameters, calculations and simulations show that the proposed matching arrangement achieves a noise figure at 0.9 GHz, which is about 0.9-dB better than the state-of-the-art solutionIEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing 12/1999;