Conference Paper

Novel μtrench phase-change memory cell for embedded and stand-alone non-volatile memory applications

Central R&D, STMicroelectronics, Agrate Brianza, Italy
DOI: 10.1109/VLSIT.2004.1345368 Conference: VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on
Source: IEEE Xplore


A novel cell structure for chalcogenide-based non-volatile Phase-Change Memories is presented. The new μtrench approach is fully compatible with an advanced CMOS technology, is highly manufacturable and allows to optimize array density and cell performance. Programming currents of 600 μA, endurance of 1011 programming cycles and data retention capabilities for 10 years at 110°C have been demonstrated. The manufacturability is proven by experimental results from multi-megabit arrays.

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Available from: Fabio Pellizzer, Jan 24, 2015
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    • "The storage element is made of (GST). The cells utilize a pnp bipolar selection device, stacked with the cell (Fig. 1) [14]. The arrays are organized in 16-bit words. "
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    ABSTRACT: Single event effects are investigated in 90-nm phase change memories. The cells are shown to be insensitive to heavy-ion strikes and will likely remain so for a few more generations. Possible physical mechanisms leading to upsets in future generations are discussed. Errors and functional interrupts, in addition to single event latch-up, were observed during read, word and buffer program due to strikes in the peripheral circuitry.
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    • "Our experimental investigation was carried out on a 180-nm 4M-cell MOSFET-selected PCM experimental chip based on theµ-trench cell architecture [7]. The memory cell is biased by applying adequate voltage levels to the selected bit-line (BL) through a high-voltage natural NMOS transistor, Y O , which operates as a source follower (Fig. 1) [8]. "
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    ABSTRACT: In this work, staircase-up (SCU) partial-RESET programming in Phase Change Memories is experimentally investigated at both the single cell and the array level. The aim of this work is to highlight advantages and drawbacks of partial-RESET programming from the viewpoint of multilevel (ML) storage, where the cell can be programmed to any among n >2 predetermined different states. Although high reproducibility of the SCU partial-RESET programming curve of a single cell has been observed, the spread over the considered array implies the need for a Program-and-Verify (P&V) approach to achieve the necessary accuracy for ML storage. The feasibility of SCU P&V partial-RESET programming is experimentally demonstrated for the case of 4 log-spaced levels within the available resistance window.
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    • "This cross-section clearly highlights the self-alignment between the GST strip and the underlying heater structure. The architecture of the storage element has been developed having small cell size, low fabrication process cost, and high performance (in particular, matching the fast random access time of NOR Flash applications) as key targets [1], [5], [7]. A further key goal when designing the memory cell architecture was minimizing the RESET current (i.e., the current required to completely amorphize the active GST material) or, equivalently, maximizing heater efficiency, which leads to better performance during GST programming. "
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    ABSTRACT: In this paper, a 90-nm 128-Mcell non-volatile memory based on phase-change Ge<sub>2</sub>-Sb<sub>2</sub>-TeB alloy is presented. Memory cells are bipolar selected, and are based on a /xtrench architecture. Experimental investigation on multi-level cell (MLC) storage is addressed exploiting the chip MLC capability. To this end, a programming algorithm suitable for 2 bit/cell storage achieving tightly placed inner states (in terms of cell current or resistance) is proposed. Measurements showed the possibility of placing the required distinct cell current distributions, thus demonstrating the feasibility of the MLC phase-change memory (PCM) storage concept. Endurance tests were also carried out. Cumulative distribu tions after 2-bit/cell programming before cycling and after 100 k program cycles followed by 1 h/150 degC bake are presented. Experimental results on MLC endurance are also provided from a 180-nm 8-Mb PCM demonstrator with the same mutrench cell structure.
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