Novel pTrench Phase-Change Memory Cell for Embedded
and Stand-Alone Non-Volatile Memory Applications
F. Pellizzer, A. Pirovano, F. Ottogalli, M. Magistretti, M. Scaravaggi, P. Zuliani, M. Tosi, A. Benvenuti,
P. Besana, S. Cadeo, T. Marangon, R. Morandi, R. Piva, A. Spandre, R. Zonca, A. Modelli,
E. Varesi, T. Lowrey*, A. Lacaita’, G. Casagrande, P. Cappelletti, and R. Bez
STMicroelectronics, Central R&D, Via C. Olivetti, 2, 20041, Agrate Brianza (Milano), Italy
*Ovonyx Inc., Rochester Hills, MI, USA + DEI, Politecnico di Milano, and IFN-CNR Sez. Milano, Milano, Italy
Tel.: +39-039-6036813, E-mail: email@example.com
A novel cell structure for chalcogenide-based non-volatile Phase-
Changc Memories is presented. The new ptrench approach is fully
compatible with an advanced CMOS technology, is highly
manufacturablc and allows to optimize array density and cell
performancc. Programming currents of 600 pA, endurance of 10“
programming cycles and data retention capabilitics for 10 years at
110°C have been demonstrated. The manufacturability is proven by
experimental results from multi-megabit arrays.
Phase-Change Memories (PCM), also called Ovonic Unified Memory
(OUM), are one of the most promising candidates for next-generation
Non-Volatile Memories (NVM). Based on the reversible structural
changes of chalcogenide materials, a fast write and read, good read
signal window, very high endurance, and an intrinsic scalability are
expected. The integration of a compact PCM cell structure and of the
chalcogenide materials and the full compatibility with an advanced
CMOS technology are key aspects to bc demonstrated together with
the optimization of the programming current [1,2]. Aim of this work
is to present a navel PCM cell architecture i) completely compatible
with a CMOS technology, either for stand-alone or far embedded
applications, ii) with reduccd programming current and iii) that can
be employed in multi-megabit array structures allowing faster
readwrite access times and longer endurance than other establishcd
Phase-Change Memory Architecture
A vertical PCM cell employing the GciSbiTei (GST) chalcogenide
alloy has been integrated into an advanced 0.18 pm CMOS
technology (Tab.1). The PCM cell is integrated adding the basic
process modules, i.e., heater and GST, between the FEOL and BEOL
blocks (Tab.2). The new key concept introduced in this architecture,
that keeps the programming current low and maintains a compact
vertical integration, is thc definition of the contact area between the
heater and the GST by the intersection of a thin vertical semi-metallic
heater and a trench, that from now on we will call “ptrench”, in which
the GST is deposited. The resulting structure is schematically
depicted in Fig.1, while TEM and SEM cross-sections are reportcd in
Fig.2. Since the ptrench can be defined by sub-litho techniques and
the heater thickness by film deposition, the cell performance can be
optimized by tuning the resulting contact area, today in the range
5000-IS00 nm’, still maintaining a good CD control. Since the full
PCM ccll is composed by a variable resistance (heatcr and GST) and
a selector device, a vertical cell architecture with a common-collector
pnp-BJT selector has been developed in order to get the small cell
sire required in high-density NVM.
constitutes thc word-line, while the emitter is connected to the bottom
electrode of the storage element (Fig.1) through the tungsten pre-
contact. The top electrode of the PCM element is with the bit-line.
The resulting layout of the dcvice is extremely compact (IOF’), with a
cell area of 0.32 pm2 (Fig.3), basically limited by the selector design
rules. This PCM architecture is also fully compatible with the use of a
The base of the pnp-BJT
C 2 2004 IEEE
MOSFET sclector (Fig.4). In this casc the resulting cell size is larger
(-40F2), but it can be easily integrated with a minimum overhead of
masks, thus bcing suitable for embedded NVM applications.
The ptrench PCM cclls have been integrated into an advanced 0.18
pm CMOS process and extensively characterized. Fig.5 and Fig.6
show the oscilloscope traces of RESET and SET programming pulses
followed by a read-out pulse. It results that thc
(amorphous phase, high resistance) can be achieved with a 40 ns
programming pulse, while to get the SET statc (crystalline phase, low
resistance) programming pulses in the rangc of 100 ns are required.
The ptrench PCM device can be programmed into the RESET state
with 600 pA (Fig.7). A difference of two orders of magnitude
between the SET and RESET resistances can be easily achieved, and
an intrinsic cndurance longer than 10” programming cycles is
reponed in Fig.8. Note that sincc the ptrench width scales with the
lithography, a continuous improvcment of power consumption is
expected in ncxt generation devices. Moreover, optimizations of the
heater material and thickness are proven to allow a reduction of the
programming current, leaving room for further improvements.
Retention capabilitics have also been assessed and an activation
energy of 2.6 eV has been mcasured. Fig.9 shows that the RESET
state can be retained at I 10°C 10 years, while data retention of more
300 years can be estimated at 85°C. Finally, the
manufacturability of the BJT-selected cell, whose I-V curves are
reported in Fig.10, has been investigatcd, showing that the wafer
distributions of programmed resistances are tight (Fig. I I). Moreover
the ptrcnch PCM cell approach has been proven using an 8Mbit
Demonstrator . Fig.12 shows the cell current distributions of the
whole 8Mbit array after SET and RESET operations. A good current
window is demonstrated providing the first experimental evidence of
the feasibility of high-density PCM.
A novel ptrench vertical PCM cell has been integrated into an
advanced 0.18 pm CMOS process. The proposed ptrench approach
allows to optimize the ccll performances demonstrating programming
currents of 600 pA, endurance of IO” programming cyclcs, and data
retcntion capabilities for 10 years at 110°C. Statistical distributions on
wafer and inside multi-megabit arrays has been reported. In particular
thc statistical data on 8Mbit arrays with a working window for SET
and RESET distributions provide a strong evidence for the feasibility
of PCM technology.
[I] S. Lai, “Currcnt status of the phase-change memory and its
future”, IEDM Tech. Dig., 2003.
 A. Pirovano et al., “Scaling analysis of phase-change memory
technology”, IEDM Tech. Dig., 2003.
 F.Bedeschi et al., “An 8Mb Demonstrator for High Density I .8V
Phase-Change Memories”, submitted to Svmp. on VLSl Circ.,
PO04 Symposium on VLSl Technology Digest Of Technical Papers
Fig.2. a) TEM cross-section along the x-direction of the contact
region between the heater and the GST and b) SEM Cross-section
alone the "-direction of a PCM array.
....... __ y-q-
Fig.1. Schematic cross-sections and top-vicw of the device StruCtUSe.
Wells im lantation
1 Passivation & Pad I
Fig.3. Schematic layout of the BJT selected
$00 ZOO 100 400 500 600 700 600 9001000
FigS. Oscilloscope traces of the RESET
programming pulse and read out.
Fig.4. Schematic layout of the MOSFET
selectcd PCM cell.
Fig.6. Oscilloscope traces of the SET
programming pulse and read out.
Table.2. Schematic process flow-chart
, o s r . n . n t.I.-.-.~
Fig.7. Programming curve (R-I) for the PCM
cell in the amorphous state.
. . r 400
Fig.10. Current-Voltage (I-V) curve for the
PCM cell with the BJT selector.
,os 10. 10' 10' lo. IO3 10. (01 10. ro' 10'. 10'. (0,'
Number d cycle^ Im
Fig.8. Cycle life for a PCM cell.
Fig.9. Data retention measured on a PCM
Resistance M I
Read Current [@I
Fig.] 1. Distribution on wafer of SET and
RESET resistances for a PCM cell with the
Fig.12. Distributions of read out currents for
an XMbit array.
2004 Symposium on VLSl Technology Digest of Technical Papers