Conference Paper

A threshold logic synthesis tool for RTD circuits

Inst. de Microelectron. de Sevilla, CNM, Sevilla, Spain
DOI: 10.1109/DSD.2004.1333337 Conference: Digital System Design, 2004. DSD 2004. Euromicro Symposium on
Source: DBLP


Functional devices and circuits based on resonant tunneling diodes (RTD) are receiving much attention since they allow high speed and/or low power operation. RTDs exhibit a negative differential resistance in their current-voltage characteristic which can be exploited to significantly increase the functionality implemented by a single gate in comparison to other technologies. In particular, they have proven to efficiently implement threshold gates which are a generalization of conventional Boolean gates. Suitable logic synthesis tools are required to handle these complex building blocks in order to translate the advantages of this emergent technology to the circuit and system levels. This paper describes an efficient approach to the automatic design of networks of threshold gates from functional specifications. Results for widely used logic functions and standard benchmark circuits are reported.

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    • "However, the main drawbacks of these methods are the number of identified functions and the fact that the assigned input weights are not always the minimum possible value. These non-minimal weights impact the final area of the TLG based circuits [2][5]. "
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    ABSTRACT: In this paper, a novel method to identify threshold logic functions (TLF) is proposed. Threshold logic is a promising alternative to conventional Boolean logic that has been recently revisited due to the suitability to emerging technologies, such as QCA, RTD, SET, TPL and spintronics. Identification and synthesis of TLF are fundamental tasks for the development of circuit design flow based on such logic style. The proposed method exploits both the order of Chow parameters and the system of inequalities, extracted from a function, to assign optimal variable weights and optimal threshold value. It is the first heuristic algorithm that does not uses integer linear programming (ILP) able to identify all threshold functions with up to five variables. Moreover, it also identifies more functions than other related heuristic methods when the number of variables is higher than five. The proposed algorithm is scalable, since the average execution time is less than 1 ms per function. Furthermore, the method always assigns the minimum weights, resulting in circuits with minimum area.
    Integrated Circuits and Systems Design (SBCCI), 2013 26th Symposium on; 01/2013
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    • "The method in [2] which generates feed forward threshold circuits takes more than a minute to synthesize even small circuits of two threshold gates. Runtime is not reported for the method in [16] and the method in [13] takes about a second for each of the benchmark circuits. "
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    ABSTRACT: Threshold logic is a powerful alternative to Boolean logic. Recently there has been renewed interest in the synthesis of threshold networks that implement logic functions. Until now, different heuristics have been proposed to generate threshold networks starting from the Boolean network of a function. These methods are essentially recombination of nodes of the Boolean network. We propose a new methodology for the synthesis of threshold networks starting from the factored form of the function. Two versions of the algorithm are proposed. One of them is shown to be optimal for a specific type of factored form. We compare our results against the previous approaches and on an average get a gate reduction of 14.14% and a delay reduction of 24%. The novelty in the work is the elimination of the use of the ILP formulation, that is extensively used by all the previous methods to detect threshold networks and to assign feasible weights.
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    • "Their algorithm then tries to reduce the number of gates by replacing the Boolean gates by threshold gates using a node collapsing algorithm. Avedillo and Quintana [24] used an exhaustive architecture search tool for the construction of threshold networks. Exhaustive results can be only applied to limited size circuits due to the exponential complexity of the problem and thus they applied their method to Boolean circuits with a fan-in max of seven generated from the SIS system. "
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    ABSTRACT: A new algorithm for obtaining efficient architectures composed of threshold gates that implement arbitrary Boolean functions is introduced. The method reduces the complexity of a given target function by splitting the function according to the variable with the highest influence. The procedure is iteratively applied until a set of threshold functions is obtained, leading to reduced depth architectures, in which the obtained threshold functions form the nodes and a and or or function is the output of the architecture. The algorithm is tested on a large set of benchmark functions and the results compared to previous existing solutions, showing a considerable reduction on the number of gates and levels of the obtained architectures. An extension of the method for partially defined functions is also introduced and the generalization ability of the method is analyzed.
    Circuits and Systems I: Regular Papers, IEEE Transactions on 12/2008; 55(10-55):3188 - 3196. DOI:10.1109/TCSI.2008.923432 · 2.40 Impact Factor
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