Page 1

ABSTRACT1

Functional devices and circuits based on Resonant Tunnelling

Diodes (RTDs) are receiving much attention since they allow high

speed and/or low power operation. RTDs exhibit a negative differ-

ential resistance in their current-voltage characteristic which can

be exploited to significantly increase the functionality imple-

mented by a single gate in comparison to other technologies. In

particular they have proven to efficiently implement threshold

gates which are a generalization of conventional boolean gates.

Suitable logic synthesis tools are required to handle these complex

building blocks in order to translate the advantages of this emer-

gent technology to the circuit and system levels. This paper

describes an efficient approach to the automatic design of net-

works of threshold gates from functional specifications. Results

on wide used logic functions and standard benchmark circuits are

reported.

1. INTRODUCTION

Resonant tunnelling diodes (RTDs) are very fast non lin-

ear circuit elements which are used in high speed low-power

circuits. Switching speeds at room temperature in the order of

one picosecond have been reported for these devices. In addi-

tion, RTDs exhibit a negative differential resistance (NDR)

region in their current-voltage characteristics which can be

exploited to significantly increase the functionality imple-

mented by a single gate in comparison to MOS and bipolar

technologies, thus reducing circuit complexity and power

consumption. Many of them rely on utilizing the latching

property of the clocked series connection of a pair of RTDs

(MOBILE) arising from their NDR characteristic. In general,

MOBILE based logic families combine the basic pair of se-

ries-connected RTDs with different three terminal devices to

achieve input-output isolation and functionality. Most report-

ed working circuits have been fabricated in III/V while Si-

based RTDs is an area of active research.

The MOBILE operating principle [1] is very well suited

to implement Threshold Gates (TGs) [2]. RTD-based TGs

have been fabricated and have demonstrated high speed and

robust operation [4], [5]. The power of the threshold gates lies

in the intrinsic complex functions implemented by such

gates, which allows for realizations that require less threshold

gates than standard boolean logic gates. A number of theoret-

ical results show that polynomial-size, bounded level net-

works of threshold gates can implement functions that require

unbounded level networks of standard logic gates In particu-

lar, important functions like multiple-addition, multiplica-

tion, division, or sorting can be implemented by polynomial-

size threshold circuits of small constant depth [3].

Translating the advantages of this emergent technology to the

circuit and system levels could be limited by the lack of automatic

synthesis procedures. Many logic algorithm exist targeting con-

ventional logic gates but few have been specifically developed for

TGs. The problem was addressed as early as the beginning of the

70’s, but unfortunately it seems that almost nothing has been done

since then. LSAT algorithm [6] inspired from techniques used in

classical two-level minimization of logic circuits, a multi-level

approach [7] and a very recent work [8] are remarkable excep-

tions.

This paper describes an efficient approach to the automatic

design of networks of threshold gates from functional especi-

fications. Set of solutions are described by discrete functions

and represented by Multi-valued Decision Diagrams (MDDs)

which are a variant of BDDs. The problem of designing a

optimum network of TGs is transformed in a satisfiability

problem. The rest of the paper is organized as follows. Sec-

tion II formally defines the concept of threshold logic and

establish the formulation of the problem of logic synthesis

for TGs on which our CAD tool relies. Section III describes

the implementation of the proposed approach. Section IV

reports experimental results. Finally, Section V gives some

conclusions.

A Threshold Logic Synthesis Tool for RTD

Circuits

María J. Avedillo and José M. Quintana

Instituto de Microelectrónica de Sevilla, IMSE-CNM,

Universidad de Sevilla, SPAIN.

Page 2

2. LOGIC SYNTHESIS BASED ON THRESHOLD

GATES

2.1 Background

A threshold gate (TG) is defined as a logic gate with n

binary input variables,

xi

, one binary output

, and for which there is a set of real numbers:

threshold T and weights , such that its input-

output relationship is defined as iff

and

tional, rather than the logical, operations. Figure 1 shows the

non-standard symbol we use for TGs.

Many CAD problems can be naturally formulated by means of

discrete functions by defining a characteristic function F which

implicitly represents the set of solutions:

otherwise [2]. Sum and product are the conven-

F(c1, c2, ..., cn) = 1 iff (c1, c2, ..., cn) is a solution

F(c1, c2, ..., cn) = 0 in othercase

where c1, c2, ..., cn are multi-valued variables which can take val-

ues from a discrete set. Thus, given F, the CAD problem is solved

by determining whether F is satisfiable, that is, whether it evalu-

ates to 1 for some input combination and in such case, obtaining

one or the complete set of such input combinations verifying F. It

is very important to efficiently realize this using a suitable repre-

sentation for F. We have resorted to MDDs that we briefly intro-

duced.

It is well known that binary boolean functions, f: Bn → Β, can

be represented by ordered Binary Decision Diagrams (BDD) [9].

A BDD is a directed acyclic graph where a Shannon decomposi-

tion is carried out in each node

BDDs can be extended to Multivalued Decision Diagrams

(MDDs) [10], [11] representing multivalued functions, f: {0, 1, ...,

k-1}n → Β. Each internal node has as many outgoing edges as dif-

ferent values can take the variables. Figure 2 shows an MDD of

the characteristic function of the relation x > y, with x and y ∈ {0,

1, 2}.

2.2 Network synthesis

Figure 3 depicts a multi-layer feed forward network of thresh-

old logic which is able to implement any n-input function f(x1, x2,

..., xn) [2].

i1 … n

,,

=

(),

y

n1+

()

w1w2… wn

,,,

y1=wixi

i1=

n

∑

T

≥

y0=

w1

w2

wn-1

wn

T

X1

X2

Xn-1

Xn

f(X1,X2, ...Xn)

Figure 1.- Threshold gate symbol.

YY

1

0

2

1

2

X

F

1

20

0

1

0

F(X, Y) = 1 if x > y; x, y ∈{0, 1, 2}

Figure 2.- MDD of x > y.

...

...

...

...

w11

.

w1n T1

w21

w2n T2

α12

w(M-1)1

α2(M-1)

w(M-1)n TM-1

α(M-2)(M-1)

α1(M-1)

wM1

α2M

α(M-1)M

TM

.

α1M

wMn

.

X1

X1

X1

X1

Xn

Xn

Xn

Xn

Wij ∈ Ζ

αlk ∈ Ζ

..

...

Figure 3.- General multi-layer feed forward network of threshold gates

f

Page 3

The problem of logic synthesis using threshold gates can be

formulated as:

Given f(x1, x2, ..., xn) determine the minimum num-

ber of threshold elements, M, required to implement f,

as well as the set of weights and threshold for each of

the gates

From the description of a function, f(x1, x2, ..., xn), the proce-

dure shown in Figure 4 builds up a multi-valued function, FredM,

such that if this function is satisfiable then can be implemented by

a network with M gates and the structure in Figure 3. Each assign-

ment of input variables satisfying FredM completely defines a net-

work implementing f. That is, specifies weights and threshold for

each gate. The problem of optimum synthesis of threshold gates

networks can be solved in an incremental way by solving a

sequence of problems, repeating the described procedure for

increasing values of M.

Given the NP nature of this problem, the search of exact solu-

tions is only practical for a low number of inputs. Circuit partition

techniques can be used and the synthesis procedure just described

can be applied to each partition. This is the strategy we have taken

in the new tool.

3. DESCRIPTION OF PROPOSED APPROACH

Figure 5 depicts the block diagram of the tool. It takes as input

the functional description of the circuit to be synthesized in

ESPRESSO or BLIF format, the ranges for the weights associated

to each of the variables as well as the ranges for each of the thresh-

olds values. The output is a netlist of threshold gates. There are

two main modules in the tool. The first is the partitioning module.

The second module is the synthesis module. It starts with an anal-

ysis step which carries out operations such as classification of

variables and identification of symmetries with the aim of simpli-

1) A multi-valued integer variable is associated to each of the weights and threshold in the network.

2) For each input combination (x1, x2, ..., xn) for which f(x1, x2, ..., xn) = 1 the following function with binary output and multi-valued input

is built up1:

3) For each input combination (x1, x2, ..., xn) for which f(x1, x2, ..., xn) = 0 the following function with binary output and multi-valued input

is built up1

4) Function FredM is built up from the conjuction of the expresions obtained in previous steps of this procedure.

1.1Each parenthesis represents the characteristic function of the corresponding relation.

WMixi

⋅

i1=

n

∑

α1M

…αM

(

1–

)M

+++TM

≥

WM

(

1–

)ixi

⋅

i1=

n

∑

α1 M1–

()

…αM

(

2–

) M

(

1–

)

+++TM1–

≥

…

W1ixi

⋅

i1=

n

∑

T1

≥

WMixi

⋅

i1=

n

∑

α2M…αM

(

1–

)M

++TM

≥

WM

(

1–

)ixi

⋅

i1=

n

∑

…αM

(

2–

) M

(

1–

)

++TM1–

≥

…

W1ixi

⋅

i1=

n

∑

T1

<

…

WMixi

⋅

i1=

n

∑

TM

≥

WM

(

1–

)ixi

⋅

i1=

n

∑

TM1–

<

…

W1ixi

⋅

i1=

n

∑

T1

<

WMixi

⋅

i1=

n

∑

α1M

…αM

(

1–

)M

+++TM

<

WM

(

1–

)ixi

⋅

i1=

n

∑

α1 M1–

()

…αM

(

2–

) M

(

1–

)

+++TM1–

≥

…

W1ixi

⋅

i1=

n

∑

T1

≥

WMixi

⋅

i1=

n

∑

α2M

…αM1–

()M

··

++TM

<

WM

(

1–

)ixi

⋅

i1=

n

∑

…αM

(

2–

) M

(

1–

)

++TM1–

≥

…

W1ixi

⋅

i1=

n

∑

T1

<

…

WMixi

⋅

i1=

n

∑

TM

<

WM

(

1–

)ixi

⋅

i1=

n

∑

TM1–

<

…

W1ixi

⋅

i1=

n

∑

T1

<

Figure 4.- Procedure to synthesize a network with M threshold gates

Page 4

fying the network synthesis. All these task are realized on the

BDD representing the function f. Then, it builds the MDDs repre-

senting the functions FredM described in previous Section. If FredM

can be satisfied, an input assignment verifying it is produced.

The building and storing of the MDD representing can be com-

putationally expensive for functions with a relatively low number

of input variables. Because of this, an strategy which transform

the problem in a collection of subproblems which can be effi-

ciently solved has been applied (search strategy 1) in our imple-

mentation. Each of these subproblem is obtained by fixing a

reduced number of he variables.

In addition, it is possible to speed up the search process without

carrying out the AND operation of the MDDs associated to the

equations corresponding to each input combination. A recursive

procedure to obtain an assignment simultaneously satisfying all

the sub-functions (search strategy 2) has been developed.

The new tool can be used to exactly solved the problem of

deriving the minimum threshold-gate network implementing a

given function if no partition is applied. Also, a particular case of

using the tool corresponds to specify the range for the weights and

for the threshold. In this way, networks of NOR gates are synthe-

sized.

4. EXPERIMENTAL RESULTS

A prototype of the tool, called LTHRES, has been imple-

mented using the MDDs’ and BDDs’ packages from SIS. It also

incorporates an standard partition algorithm from SIS [12]. An

specific one aiming at optimize for threshold network implemen-

tation the partition obtained is currently under development.

Table I shows the results obtained for some logic functions

widely used in digital design. The tool has been applied to obtain

minimum networks of TGs implementing them. There have been

included columns for the number of inputs (I), the number of out-

puts (O), the minimum number of TGs in a network implement-

ing the functions and the time (seconds in a SparcStation 10)

LTHRES consumes in obtaining the complete set of solutions and

a single solution with different search strategies. The application

of search strategies 1 and 2 is advantageous for the examples with

more inputs and outputs.

Table II compares threshold based realizations with implemen-

tations using a conventional cell library. Conventional multi-level

implementations have been generated within SIS. Optimization

has been performed applying script.rugged. Technological map-

ping has been done by an algorithm targeting area minimization

(map - m 0 de SIS). The used library comprises 13 gates: in,

nand2, nand3, nand4, nor2, nor3, nor4, and2, or2, aoi21, aoi22,

oai21 y oai22. The resulting implementations have been com-

pared in terms of number of gates and logic levels. In order to esti-

mate the complexity of implementing these circuits with less

levels, the number of product terms (tp) in a two-level implemen-

tation obtained with ESPRESSO is also included.

Finally, Table III compares threshold and conventional realiza-

tions for a set of standard benchmark circuits. Both implementa-

tions have been obtained applying identical combinational

optimization. In the partitioning carried out to derive threshold

network the number of inputs per partition has been limited to 5.

Even without an specific partitioning algorithm good results are

obtained in spite of the fact that a specific partition algortihm is

not being applied.

Comparisons to other existing tools have not carried out. It has

no sense in the case of LSAT which is aimed at two-level imple-

mentations. Concerning the multi-level approach from [8], it has

not been possible as the tool is not available. Direct comparison of

data reported is not significant because several reasons. First,

because there are not enough details on combinational optimiza-

tion to be able to reproduce it. Second, reported results constraint

fan-in of the threshold gates to three.

SPECIFICATION

BDDs

SOFTWARE

MDDs

SOFTWARE

NETLIST

PARTITION

Figura 5.- Block diagram of new tool

SYNTHESIS

Page 5

a.- Obtaining the complete set of solutions

b.- Obtaining the complete set of solutions with search strategy 1.

c.- .Obtaining a single solution with search strategy 1.

d.- Obtaining a single solution with search strategy 2.

e.- Obtaining a single solution with search strategy 1 and 2.

time seconds in Sparc10

Table I: Synthesis of minimum networks with different options of LTHRES

# I # O

#

gates

a

time (s)

b

time (s)

c

time (s)

d

time (s)

e

time (s)

par33121’9 2’331’32’3

par4413263’2408 41493202

par5513669 11601186 3731130

d.ff4126’6 10’410’43’26’9

d2.ff4127’1 10’210’12’85’6

2de5512 40’667 673078

add437 581573219 95 101

addc537 > 1200 481479309 182

Table II:Comaprison of threshold and conventional realization

# I# O

Thres.

# gates# levels

Conv.

# gates# levels

Two-Levels#

tp

par33122444

par44133768

par551338816

d.ff4122332

d2.ff4122332

2de55122 155 10

add4372137 11

addc5372 16823