Conference Paper

Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
DOI: 10.1109/ISCAS.2004.1329261 Conference: Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on, Volume: 2
Source: IEEE Xplore

ABSTRACT This paper presents a new macroblock (MB) pipelining scheme for H.264/AVC encoder. Conventional video encoders adopt two-stage MB pipelines, which are not suitable for H.264/AVC due to the long encoding path, sequential procedure, and large bandwidth requirement. According to our analysis of encoding process, an H.264/AVC accelerator is divided into five major functional blocks with four-stage MB pipelines to highly increase the processing capability and hardware utilization. By adopting shared memories between adjacent pipelines with sophisticated task scheduling, 55% of the bus bandwidth can be further reduced. Besides, hardware-oriented algorithms are proposed without loss of video quality to remove data dependencies that prevent parallel processing and MB pipelining. The H.264/AVC Baseline Profile Level Three encoder, which requires computational complexity of 1.8 tera-instructions per second (TIPS), is successfully mapped into hardware with our MB pipeline scheme at 100 MHz.

  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper proposes an AVS/H.264 dual mode video decoder targeted at high definition video applications. The proposed design is compatible to decode H.264-BP/MP/HP and AVS-JP bit-streams with optimization on both system and component levels. On system level, we simplify the control of H.264 MBAFF coding, and reduce buffer size for storing prediction data. On component level, we improve the throughput in bit-stream decoding and integrate AVS/H.264 processing units together to reduce hardware cost. Through the optimization techniques, the proposed design can achieve real-time HD1080 (1920x1088@30Hz) decoding at 150MHz.
  • [Show abstract] [Hide abstract]
    ABSTRACT: Rate Control plays an important role for video coding especially in video streaming applications with bandwidth constraints. In this paper we propose a new H.264 Basic-Unit (BU)-level rate control algorithm facilitating low power hardware realization. The goal of the proposed algorithm is to achieve low computational complexity while maintaining comparable video quality at low bitrates, which reduces up to 96% of computational complexity as compared to H.264 reference software JM. The proposed algorithm is very suitable for the realization in both embedded systems as a software solution and low power systems as a hardware solution.
  • [Show abstract] [Hide abstract]
    ABSTRACT: Motion Estimation is the most complex part in H.264 encoder which takes more than 90% time in baseline profile while making test encoding using JM15.1. In the motion estimation stage, macro block cost calculation is very important for motion vector prediction and bit stream estimation. As a new characteristic introduced in H.264, Fractional ME is an essential part for improving encoder efficiency. In this paper we tried to promote another order of progress structure, and based on the rearranged structure stages we analyzed the MB cost data. Taking the mathematical characteristics of cost distribution while calculating SATD, we can make an idea of how to reduce the complexity. Thus, further reduction of hardware cost can be estimated.


Available from