Conference Paper

A power constrained simultaneous noise and input matched low noise amplifier design technique

Inf. & Commun. Univ., Daejeon, South Korea
DOI: 10.1109/ISCAS.2004.1328995 Conference: Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on, Volume: 4
Source: IEEE Xplore

ABSTRACT In this paper, very simple and insightful sets of noise parameters expressions for a power-constrained simultaneous noise and input matching (PCSNIM) CMOS LNA design technique are newly introduced. Based on the noise parameters expression, the design principle, advantages, and limitations are clearly explained. The proposed LNA is optimized for low voltage, low power 900 MHz Zigbee applications based on 0.25 μm CMOS technology. Measurement results show a power gain of 12 dB, NF and NFmin of 1.35 dB, and IIP3 of -4 dBm while dissipating the DC current of 1.6 mA (only 0.7 mA for NMOS transistor) at a supply voltage of 1.25 V.

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