Low-voltage linear voltage regulator suitable for memories

Abstract

In this communication a low-voltage linear voltage regulator in CMOS technology is presented. It is based on a two class-AB gain stage and, hence, does not suffer from internal slew-rate limitation when very large load capacitances are used. The linear regulator suitable for memory application was designed in a 0.35 μm standard CMOS technology. The regulator can work with a no-regulated input voltage in the range from 1.3 V to 3 V providing a regulated voltage of 1 V with a load capacitance of 2.2 nF.

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LOW-VOLTAGE LINEAR VOLTAGE REGULATOR SUITABLE FOR MEMORIES
W. Aloisi, S.M. Billé, G. Palumbo
DIEES - Università di Catania
V.le A. Doria, 6
Catania, I-95125, Italy
ABSTRACT
In this communication a low-voltage linear voltage regulator in
CMOS technology is presented. It is based on a two class-AB
gain stage and, hence, does not suffers from internal slew-rate
limitation when very large load capacitances are used. The
linear regulator suitable for memory application was designed in
a 0.35 µm standard CMOS technology. The regulator can work
with a no-regulated input voltage in the range from 1.3 V to 3 V
providing a regulated voltage of 1 V with a load capacitance of
2.2 nF
1. INTRODUCTION
Over the last decade, the design of analog circuits operating with
low supply voltages (1.5 V or less) has become a mandatory
target in most digital and analog CMOS integrated circuits [1],
[2]. Unfortunately, in mixed-signal environments, the trend
towards lowering the power supply of digital circuitries often
sacrifices their analog counterparts in terms of speed, noise
requirements and linearity. This means that new analog circuit
solutions have to be found to guarantee improved or even
traditional performance while using standard CMOS processes.
The core of a linear voltage regulator which also define its
main feature is an operational amplifier (Op-Amp). In particular,
the Op-Amp, unlike the simple transconductance amplifier,
includes an output stage capable of driving low load resistances
as well as large load capacitances [3]-[7]. Moreover, to obtain
high gains, two or more transconductor stages are used and
Miller strategy is used to provide compensation [8]. In order to
overcome speed limitation deriving from inner slew rate a low-
voltage class-AB transconductor must be adopted [9].
In this communication, a linear voltage regulator that works
with a 1.5-V power supply is presented. The regulator exploit the
benefit of a two class-AB gain stages and, hence, does not
suffers from slew-rate limitation. The linear regulator is suitable
as read bit-line voltage regulator in memories application and
was designed in a 0.35 µm standard CMOS technology.
2. LINEAR VOLTAGE REGULATOR
A linear voltage regulator topology, capable of driving both low
load resistances and large load capacitances is shown in Fig. 1. It
is worth noting that, the core of regulator consist of an Op-Amp
in a voltage follower configuration, which define the main
characteristics of the whole regulator.
RL
vout
CL
VREF
iP
Figure1. Schematic of voltage regulator.
In the following we exploiting the main blocks needed to design
the Op-Amp for such regulator.
2.1 Input Stage
The adopted solution for the input stage is shown in Fig.2 and it
is based on a novel class AB topology [9]. The stage consists of
a main source-coupled differential pair (MDP), which is made
up by transistors M1a and M1b biased with transistors M2a-
M2b, two driver differential pairs (DDPa and DDPb), which
allow the circuit to work in class-AB, and a stacked mirror
structure based on simple current mirrors, which performs the
differential to single conversion.
M3a
vIN-
vIN+
M1a M1b
vIN-
vIN+ vIN-
vIN+
VDD
VDD
M7a M7b
M2a M2b
iSS
M3b
M5b M4b M4a M5a
M6b
M6a
M6c
M7c
M8 M9
M10
vOUT
iOUT
IB
Figure 2. Class-AB Input stage.
Assuming aspect ratios of transistors Mia to be set equal to
aspect ratios of transistors Mib (i = 1,2,..7), let us define
32ββ=
k
(1)
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54ββ=
h
(2)
897 10
ββββ==
m
(3)
being
()()i
ox
LWC
2
µβ =
and with the usual meaning of all
other parameters. According to analysis in [9], in quiescent
condition, the current of the MDP, ISS, and the current in the
final branch, ID9,10, result
()B
I
1
SS
hkI
2
+=
(4)
()B
I
1
D
hmkI
10 , 9
+=
(5)
Let us analyze the large signal circuit behavior, that is for
vIN+ ? vIN–. To this aim we define the differential input and
output signal as vD = vIN+ – vIN– and iOUT = iD10 –iD9, respectively.
Referring to Fig. 2, the output current, iOUT, is
()
2
D
1
4
1
1
1414
B
DOUT
ivk
I
β
hkvm
⎟⎟
⎠
⎞
⎜⎜
⎝
⎛
−++=
β
β
β
(6)
which demonstrates iOUT not limited by the bias current.
Specifically, setting
k
4
41
<ββ
(7)
we get iOUT to increase with vD in a quasi-quadratic behavior.
2.2 Output Stage
The adopted output stage was introduced in [4] and is depicted
in Fig. 3. It consists of a push-pull output pair, MN and MP and
two adaptive loads made up of transistors M15-M16 and M17-
M18 driven by transistors M13 and M14, respectively. Two
voltages, VB1 and VB2 are required to bias the adaptive load while
the whole stage is biased by current generators, IB1 and IB2.
Finally, transistors M11 and M12 operate the phase inversion
required for frequency compensation.
A
M17
IB2
VDD
vin
vout
iout
M11
M12 M13
M15
M14
B
VB2
VB1
IB1
M16
M18 MP
MN
C
Figure3. Class-AB output stage.
Consider the circuit in Fig. 3 with
1816
ββββ
PN
n
==
(8)
under quiescent conditions assuming all the transistors to be in
saturation region, the overall feedback imposes IDMN = IDMP = IQ.
As a consequence, due to (8), both the drain currents of M18 and
M16 are forced to IQ/n. Moreover,
()
1413
1
βαβ+=
(9)
IIB=
1
(10)
IIB
)1 (
2
α+=
(11)
as suggested in the original work, leads to ID15 = ID18 = αI and,
thus we get
InIQ
α=
(12)
In [4], α was set to about 0.2 in order to obtain a good trade-off
between linearity and quiescent current sensitivity. However,
this design strategy is not efficient in terms of distortion due to
the different operating condition of M13 and M14. In fact, their
different aspect ratios and bias currents leads to a high second
harmonic factor.
A better design strategy with a remarkable improvement in
terms of linearity, can be obtained by designing M13 and M14
with the same aspect ratio while carrying the same current. In
fact, imposing
1413
ββ=
(13)
IIB
)1 (
1
α−=
(14)
IIB
)1 (
2
α+=
(15)
instead of (9)-(11), not only let us achieve the goal of reducing
distortion but also requires less bias current while maintaining
the same quiescent current, IQ, defined in (12). Indeed, it is easy
to verify that, for the same IQ, the quantity IB1 + IB2 is reduced by
αI.
Obviously, currents in M18 and M16 remain the same, too,
while the current flowing through M13 and M14 is now set to
I
II
I
BB
D
=
+
2
=
21
14, 13
(16)
As far as the large signal behavior is concerned, the stage
exploits the adaptive load made up of M15-M16 and M17-M18
to work in class-AB. In fact, in quiescent conditions, all the
transistors are in saturation region, hence, the resistive loads
connected to node A and B are small. When the input level
increases, for example in the negative direction, transistor M11
delivers an extra current to M12 which is subsequently mirrored
to both M13 and M14. The extra current in M13 flows through
M17-M18 and, consequently, the gate of M18 is pulled down,
while its drain voltage tends to VDD because of the presence of
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M17 whose gate-source voltage increases, too. If VB2 is set
properly, M18 enters the triode region thus causing the overall
resistive load at node A to increase as well. In such a situation,
any small increment of current from M13 causes large swing at
node A and provides the adequate overdrive to the gate of MP.
In the meantime, once the extra current in M14 equals IB2,
transistors M15, M16 and, consequently, MN turn off. Therefore
the load is supplied by MP only. A complementary behavior is
followed when the input level increases in the positive direction.
It is worth noting that there is a different behavior in class-B
mode. Specifically, when the input level increases negatively, the
current which flows in M17-M18 is supplied by M13 and,
hence, is not limited. Instead, when the input level increases in
the opposite direction, the current that flows in M15-M16 is
bounded by the current generator IB2. However, in this condition,
the class-B operation is guaranteed by the adaptive load
performed by M15-M16 which turns node B into a high
impedance node. Anyway, in order to make up for the current
limitation given by IB2, a high bias current is required to
guarantee the proper overdrive to output transistor MN.
As mentioned above, both voltages VB1 and VB2 must be set
so that, in bias condition, drain-source voltages of both M16 and
M18 remain close to their respective saturation voltage. In this
manner, a small increment of drain current in M16 (M18) causes
VGS16(18) to increase and VDS16(18) to decrease, thus immediately
entering the triode region. Therefore, the stage must satisfy the
following design constraints
DSsat TnB
VVV
2
1
+=
(17)
DSsat TpDDB
VVVV
2
2
−−=
(18)
being VDSsat the saturation drain-source voltage for the transistors
M16 and M18.
2.3 Overall Buffer
The overall voltage buffer is shown in Fig. 4. It is a double-stage
gain made up of the class-AB input and output stage previously
described.
To guarantee stability in closed-loop configuration, a Miller
compensation was used. Thus capacitor CC and the equivalent
resistance at the output of input stage, ro9,10, determine the
dominant pole of the amplifier, according to
LP oN
r
MoutCo
D
RGCr
,10, 9
1
≈
ω
(19)
where roN,P is the equivalent resistance of output stage and GMout
represents the equivalent transconductance of the output stage,
that is
12
14, 13
11
2
m
m
mMout
g
g
ngG
=
(20)
The DC loop-gain, T(0), is
LPoN
r
utMom
RGrmgT
,010, 91
) 0 (
=
(21)
and, consequently, the amplifier gain-bandwidth product, ωGBW,
results
C
m
GBW
C
mg
1
=ω
(22)
Assuming CL larger than other parasitic capacitors, the second
pole, ω2, of the loop gain results
L
LMout
C
RG
1
2
+
=
ω
(23)
Since the gain-bandwidth product, ωGBW, is independent of the
load resistor, RL, and the second pole, ω2, increases with 1/RL, it
is apparent that the worst case for the amplifier stability occurs
when the resistive load, RL, is absent. Hence, in order to
guarantee an adequate phase margin, ϕm, the compensation
capacitor CC must be set to
Mout
m
mLC
G
mg
CC
1
tanϕ=
(24)
Resistor, RC, allows to eliminate the right half-plane zero and is
set equal to
Mout
G
1
.
M3a
vIN+
vIN-
M1a M1b
vIN+
vIN- vIN+
vIN-
VDD
VDD
M7a M7b
M2a M2b
iSS
M3b
M5b M4b M4a M5a
M6b
M6a
M6c
M7c
M8 M9
M10
vOUT
iOUT
IB
M11
M12
M13 M14
M15
M16
M17
M18
MN
MP
M24
M19
M20 M21
M22
M23
M25
M26
RC
CC
Figure 4. Low-Voltage Op-Amp.
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Page 4

3. SIMULATION RESULTS
A linear regulator suitable as read bit-line voltage regulator in
memories application was designed in a 0.35 µm standard
CMOS technology. Main process parameters are kn = 175
µA/V2, kp = 60 µA/V2, VTn = 0.55 V and VTp = –0.65 V. The
schematic of regulator is depicted in Fig.1 and amplifier
component values are reported in Tab. I. The regulator can work
with a no-regulated input voltage in the range from 1.3 V to 3 V,
and allows two mode of operation. Specifically, in stand-by
mode, the regulated output voltage is 1.1 V and the average
output current is 20 µA (i.e. a resistive load of 55 kΩ), while in
operative-mode, the regulated voltage is 1 V with an average
output current of 9 mA.
The circuit to implement the voltage reference, VREF, is
based on a canonical band-gap structure followed by a voltage
buffer and a resistive network that allows to set the required
voltage.
In order to emulate the current request of memory a
particular load output current was considered. Specifically, a
step current of 50 mA in 4 ns modeling the cell memory
selection, and a step current of 10 mA in 20 ns represents the
current of sense amplifier needed in read operation. To reduce
memory access time, a required key feature is a very fast
recovery of the regulator output voltage, that is, when a new
word-line is selected, the desired value of voltage has to be
provided within a specified ripple in a very short time. To this
purpose we shall focus the attention on the regulator response to
the output load current, rather than on the common regulator
performances. Fig. 5 shows the simulated regulator response to
the current memory request. When starts the operative mode, the
output voltage falls to 920 mV and reaches the steady-state
condition after 80 ns. In such a case the voltage ripple is about ±
50 mV with an average voltage of 1V. It is worth noting that, the
current consumption of the whole regulator is about 40 µA.
Output Voltage (V)
Load Current (A)
Time (s)
Figure5. Regulator response to the current memory request.
TABLE I. Component values for the Op-Amp
COMPONENTVALUECOMPONENT VALUE
M1 1/12
7/0.3
36/0.3
18/0.3
7/1
12/1
4/1
48/1
144/1
21/0.3
5/0.3
M20
M21
M22
M23
M25
M26
MN
MP
RC
CC
RL
28/1
42/1
14/1
1/1
8/1
2.3/0.3
280/0.3
1050/0.3
2.5 kΩ
140 pF
55 kΩ
M2, M3
M4
M5
M6, M19
M7
M8, M24
M9
M10
M11
M12
M13, M14
M15, M16
M17, M18
40/0.3
CL
2.2 nF
150/0.3
IB
0.5 µA
4. REFERENCES
[1] B. Hosticka, W. Brockherde, D. Hammerschmidt, R.
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