Fully-integrated DECT/Bluetooth multi-band LNA in 0.18 μm CMOS

Abstract

The design of a multi-band low noise amplifier (LNA) is the first obstacle towards the design of a multi-standard receiver. In this paper, an approach for the design of a multi-band LNA for DECT and Bluetooth is presented. The formula for a minimal noise factor of a LNA, that takes into account the finite quality factor of the inductors is derived and the full design procedure that facilitates the design of a fully integrated LNA is given. The main advantages of the presented multi-band LNA are: high level of integration, reduced chip area by using only one integrated inductor, while the other is implemented as a bond-wire, input matching at two frequencies while having low noise figure, moderate voltage gain and good linearity. In DECT mode the simulated LNA performance is: NF = 2.2 dB, gain = 17 dB, IIP3 = 0.5 dBm, with a current of 8 mA, while in Bluetooth mode the LNA achieves: NF = 2.3 dB, gain = 15 dB, IIP3 = 3 dBm, with a current of only 4 mA.

Full text

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FULLY-INTEGRATED DECT/BLUETOOTH MULTI-BAND LNA
IN 0.18 µm CMOS
Vojkan Vidojkovic, Johan van der Tang, Eric Hanssen, Arjan Leeuwenburgh∗and Arthur van Roermund
Eindhoven University of Technology, E.H. 5.28, P.O.Box 513, 5600 MB, Eindhoven, The Netherlands
∗National Semiconductor, Het Zuiderkruis 53, 5215 MV, ’s-Hertogenbosch, The Netherlands
ABSTRACT
The design of a multi-band low noise amplifier (LNA) is the first
obstacle towards the design of a multi-standard receiver. In this pa-
per, an approach for the design of a multi-band LNA for DECT and
Bluetooth is presented. The formula for a minimal noise factor of a
LNA, that takes into account the finite quality factor of the inductors
is derived and the full design procedure that facilitates the design of
a fully integrated LNA is given. The main advantages of the pre-
sented multi-band LNA are: high level of integration, reduced chip
area by using only one integrated inductor, while the other is im-
plemented as a bond-wire, input matching at two frequencies while
having low noise figure, moderate voltage gain and good linearity.
In DECT mode the simulated LNA performance is: NF = 2.2 dB,
gain = 17 dB, IIP3 = 0.5 dBm, with a current of 8 mA, while in
Bluetooth mode the LNA achieves: NF = 2.3 dB, gain = 15 dB,
IIP3 = 3 dBm, with a current of only 4 mA.
1. INTRODUCTION
The wireless market is changing very rapidly. Pushed by the cus-
tomer requirements, new systems for wireless communications are
emerging very fast. In order to increase flexibility on the market
and functionality of RF transceivers, RF designers are pursuing so-
lutions for cost-effective multi-standard transceivers. The feasibility
of a multi-standard receiver is to a great extent influenced by the
feasibility of a multi-band LNA. The difficulty in the design of a
multi-band LNA comes from the fact that it has to provide functions
as: input matching at different frequencies, adaptivity in order to sat-
isfy different set of specifications, low noise figure (NF), high gain
and good linearity, which are mutually dependent. Basically, they
depend on the design parameters in a way that a set of design param-
eter values, that improves one function, will deteriorate the others.
As a consequence, a trade-off must be made in order to achieve sat-
isfactory overall performance. Adding the requirement for a high
level of integration and avoiding the need for external discrete com-
ponents and reducing the costs, makes the LNA design even more
difficult.
The first step towards a high performance multi-band LNA is topol-
ogy selection. One possibility is to use the common-gate stage in
order to realize a wide-band LNA. The advantage of this approach is
that the input impedance is equal to 1/gm, where gmis the transcon-
ductance of the MOS transistor, but the disadvantage is rather high
minimum NF of 2.2 dB, that can be achieved [2]. For short chan-
nel devices a much worse minimal NF can be expected because γ
is much greater that one [2]. In [3], a new wide-band LNA topol-
ogy, that uses noise cancellation in order to reduce NF, is pre-
sented. Again, a rather high NF of 4.3 dB is achieved. While all
wide-band LNA topologies exhibit rather a high NF, a much lower
NF can be achieved with a narrow-band LNA that is based on the
inductively-degenerated common-source stage. Based on this topol-
ogy, in [4], a concurrent multi-band LNA is presented with NF of
2.3 dB. Also in [5], the same approach is applied and the achieved
NF is around 1 dB. Obviously, a LNA based on the inductively-
degenerated common-source stage(see Fig.1) can achieve alow NF.
This is the reason why this topology is selected. The cascode con-
figuration is used in order to increase the reverse isolation.
M2
M1
Ls
Lg
Vdc2
Vout
Rd
Vrf
Vdc1
Vdd
Figure 1. Inductively-degeneratedcommon-source LNA
The next step in the LNA design is to clearly specify design goals.
The first is to find a minimum NF that the LNA can achieve with a
certain power consumption, the second is to make the trade of be-
tween the minimum NF and full integration, and the third is to find a
way to realize the multi-band operation without degrading the LNA
performance, compared to a single-band LNA.
This paper is organized as follows. In section 2, LNA design con-
siderations are discussed. The full design procedure is presented in
section 3. In section 4, a design example is given. The multi-band
LNA for DECT and Bluetooth is presented in section 5.
2. DESIGN CONSIDERATIONS
An inductively-degenerated common-source LNA is depicted in
Fig.1. Its input impedance can be expressed by (1).
Zin= s(Ls+Lg)+
1
sCgst
+gm
Cgst
Ls
(1)
where, Cgstis the total capacitance between the gate and the source
of the transistor M1, gmis the transconductance of the transistor M1,
and s = jω. In order to provide a real input impedance of 50 Ω, the

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imaginary part of (1) must be equal to zero:
ω(Ls+Lg)−
1
ωCgst
= 0 (2)
Substituting (2) into (1), the input impedance becomes:
Zin=
gm
Cgst
Ls
(3)
The noise factor (F) of the LNA depicted in Fig.(1) can be calculated
by (4).
F = 1+1
Rs(ωLg
QLg
+ωLs
QLs
)+γgd0Rs(ωCgst
gm
)2+(ωLs)2
RsRd
(4)
where, Rsis the source resistance (Rs= 50 Ω) and gd0is zero bias
drain conductance. The finite quality factors of the inductors Lg
and Ls (QLg= ωLg/Rg and QLs= ωLs/Rs, where Rg and Rs are
series parasitic resistances of the inductors Lg and Ls), the channel
thermal noise of the transistor M1 and the thermal noise from the
load resistor Rdare taken into account.
The linearity of an inductively-degenerated common-source LNA is
proportional to the overdrive voltage of the transistor M1, when the
transistors M1 and M2 are biased in the saturation and kept far from
the triode region [6]:
IIP3 ≈Vgs−Vt
whereVgsis the voltage between gate and source of the transistor M1
and Vtis the threshold voltage.
(5)
The transconductance of the transistor M1 can be calculated using
(6).
gm=
Vdd(Vgs−Vt)
where Pdis power dissipation and Vddvoltage supply.
2Pd
(6)
The equations (2), (3), (4), (5) and (6) are thecore of the LNA design
and the main questions is how to determine the design parameters:
theaspect ratioW/L of thetransistor M1, Lg, Lsandbiasing voltages
(Vdc1 andVdc2) in order to achieve the design goals. It can be done
in the following way. In order to simply the equations and the design
procedure a factor n will be introduced. The factor n is the ratio of
the inductances Lg and Ls:
n =Lg
Ls
(7)
Combining (7) with (2), (3) and (4) the following LNA design equa-
tions can be written:
?
?
?
Rs
1+ωLs
Rs
QLg
(ωLs)2
RsRd
Ls
=
Rs
(n+1)gmω2
gm
(n+1)Rsω2
(8)
Cgst
=
(9)
Gain
=
(n+1)gm
Rd
(10)
F
=(
n
+
1
QLs)+γgd0
gm
1
n+1+
(11)
Substituting (8) into (11), the final formula for the noise factor can
be obtained:
?
F
=
1+
1
gmRs(
n
√n+1QLg
+
1
√n+1QLs
)+
γgd0
gm
1
n+1+
1
(n+1)gmRd
(12)
Analyzing (12) an important remark can be made: for a given gm
there is a value of n that gives minimal noise factor (Fmin). In order
to prove that, the first derivative of F over n has been derived:
dF
dn
=
1
√gmRs(
γgd0
gm
1
QLg
1
n+2
2?(n+1)3−
(n+1)2gmRd
1
2QLs
?(n+1)3)−
(n+1)2−
1
(13)
For n = noptthat satisfies equation 14,dF
dn= 0.
(n+2)√n+1
2QLg
−
√n+1
2QLs
= (γ +
1
gmRd)?gmRs
dn> 0. So, minimum F is
(14)
For n < nopt,dF
obtained when n = nopt. Equation (14) can be simplified and nopt
can be expressed by (15).
dn< 0 and for n > nopt,dF
n = (4Q2
Lgγ2gmRs)
1
3
(15)
Substituting (15) into (8), (7), (10) and (12), the following equations
can be obtained:
Fmin
=
1+
?
1
gmRs((4Q2
Lgγ2gmRs)
QLg
1
6
+
1
QLs(4Q2
1
Lgγ2gmRs)
1
6
)+
γgd0
gm
?
?
?gm
1
(4Q2
Lgγ2gmRs)
Rs
1
3
+
Rdgm(4Q2
Lgγ2gmRs)
1
3
(16)
Ls
=
gmω2(4Q2
Lgγ2gmRs)
1
3
(17)
Lg
=
?
?
?(4Q2
Rs(4Q2
Lgγ2gmRs)
gmω2
1
3Rs
(18)
Gain
=
Lgγ2gmRs)
1
3Rd
(19)
Equations (16), (17) and (18) are very important because they ex-
press Fmin, the inductances Ls and Lg as a function of the transcon-
ductance of the transistor M1, and in that way as a function of the
power consumption (see (6)) and the quality factors of the inductors
Lg and Ls. From the equations (16), (17) and (18) the following
important conclusions can be drawn:
• A lower Fmincan be obtained by increasing gm, which in turn
can be obtained by a higher power consumption (see (6)).
• Better quality factor of the inductors Lg and Ls improves Fmin.
• The chip area can be reduced by reducing the values of the
inductances Lg and Ls. This can be done by increasing gm,
which actually means by increasing the power consumption.
• A higher voltage gain can be obtained by increasing gm, which
means by increasing the power consumption and by increasing
the value of the load resistor (Rd).
These conclusions provide important insight that will be used to im-
prove the LNA performance and to find its limitations.

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3. DESIGN PROCEDURE
Based on equations (8), (9), (7), (10), (12) and (14), a clear and
simple LNA design procedure can be derived. The design steps are
the following:
1. Choose a starting value for the overdrive voltage (Vgs−Vt).
Usually the overdrive voltages of 150 mV to 200 mV are
enough to provide moderate linearity (IIP3 of around 0 dBm
can be expected, see (5)).
2. Based on a given power budget (Pd), determine the aspect ratio
W/L of and the transconductance (gm) of thetransistor M1(see
(6)).
3. Calculate noptthat gives minimum noise factor (see (14)).
4. Calculate the value of inductor Ls ( see (8)).
5. Calculate the value of inductor Lg ( see (7)).
6. Calculate the value of the total gate-source capacitance (Cgst)
that is necessary to satisfy the matching condition (see (9)).
7. In the case that the intrinsic gate-source capacitance of the
transistor M1 (Cgsint) is not big enough to satisfy the match-
ing condition, then it is necessary to determine the external ca-
pacitance that must be placed between gate and source (Cgsext)
in order to have input matching.
Cgsext=Cgst−Cgsint, where Cgsintcan be obtained by the simu-
lations.
8. Calculate Rdfor the required voltage gain, while making sure
to provide enough voltage room for the cascode transistor M2
to operate in the saturation region (see (10)).
9. Determine theaspect ratio(W/L ) of the cascode transistor M2
making sure to provide enough voltage room for the transistor
M1 to operate in the saturation region
10. Check theDC operating pointsand theDC voltagesinthe LNA
in order to ensure the operation of the transistors M1 and M2
in the saturation region and check the LNA performance (NF,
voltage gain, IIP3). If the specifications are not met then use
the presented insight into the LNA operation to repeat the de-
sign procedure (possibly more power is needed).
It can be calculated as:
In order to design a fully-integrated LNA one additional step must
be made. It is beneficial to implement Lgas a bond-wire.This gives a
high quality factor (more than 20 can be achieved at 2 GHz [7]), that
improves the NF. A typical bond-wire inductance is 1 nH/mm and
the inductance value that can be realized depends on the IC pack-
age size and the die position in the package. Problems can occur if
the inductance Lg that gives Fmin is to big to be implemented as a
bond-wire. The ratio of the inductance implemented as a bond-wire
(Lgbond) and one that provides Fmin (Lgopt) can be expressed as:
?
nbond+1
Lgbond
Lgopt
=
n2
bond
nopt+1
n2opt
(20)
So, having the maximum inductance value that can be implemented
as a bond-wire (Lgbond) and using (20), nbondcan be calculated. The
noise factor will be deteriorated but this is the cost that must be paid
for a full LNA integration.
Applying the presented design procedure, two design goals can be
achieved: a minimal noise factor and full integration of the LNA. It
also offers a method to determine all LNA design parameters. De-
sign methodologies presented in [1] and [4] offer noise figure opti-
mization techniques but without the possibility to determine all LNA
design parameters. Hence, the presented design procedure is advan-
tageous, and facilitates LNA design.
4. DESIGN EXAMPLE
Using the presented design procedure an inductively-degenerated
common-source LNA (see Fig. 1) is designed in 0.18 µm CMOS
technology and simulated in SpectreRF. The current is limited to
8 mA. Taking the biasing voltage (Vdc1) of 700 mV (this gives
the overdrive voltage of 200 mV), and the aspect ratio of W/L =
200/0.18, gmof 70 ms andCgsint= 348 fF are obtained. Using (14),
the factor n that gives Fminis calculated: nopt= 14. Following fur-
ther the presented design procedure the inductances and the external
gate-source capacitance are calculated: Lg= 8 nH, Ls= 0.57 nH
and Cgsext= 462 fF The quality factor of the inductor Ls is taken to
be QLs= 5 at 2 GHz, which is realistic value for integrated inductor
and the quality factor of the inductor Lg is taken to be QLg= 10 at
2 GHz because it is intended to be implemented as bond-wire. Al-
though higher bond-wire quality factor can be achieved [7] a quality
factor of 10 is used taking into account the process spread and the
production margin. Using the SpectreRF simulator a NF of 1.3 dB
is obtained.
gm=70 ms
opt
n
gm=82 ms
gm=44 ms
Ls=0.51 nH
Lg=7.7 nH
1.2
1.3
1.4
NF [dB]
1.1
Ls=0.57 nH
Lg=8 nH
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.1
2.2
2.4
2.6
02468 1012 1416 1820 22
n
calculated
Ls=0.78 nH
Lg=9.4 nH
Figure 2. Simulated noise figure as a function of n
In order to check the validity of the presented theoretical consid-
erations, the design procedure and the simulations are repeated for
different values of the parameter n and of the transconductance
(gm).The results are presented in Fig. 2. As it can be seen from Fig.2
the minimal noise factor of 1.3 dB for gmof 70 ms is achieved for
nopt= 14, which corresponds to the calculated value of nopt. Com-
paring Fminfor different gmin Fig.2, it is clear that Fminimproves
with higher gm, which means with higher power consumption. Com-
paring the values of inductances Lg and Ls for different gm, it can be
seen that they decrease (yielding reduced chip area) when gmand
power consumption increase. Comparing the conclusions based on
the theoretical considerations and observations based on the simula-
tion results, full matching is achieved. The external gate-source ca-
pacitance can be implemented as MIM capacitor, which has a very
high quality factor. In that way, NF deterioration is avoided.
5. MULTI-BAND LNA
The fact that an external gate-source capacitance (Cgsext) is used to
obtain input matching can be exploited in order to design a multi-
band LNA for DECT and Bluetooth. First, the LNA is designed to
operate in DECT mode because DECT specifications are higher than

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Bluetooth specifications. The idea is to use the same coils (Lg and
Ls), the same transistors M1 and M2 and by changing the value of
external capacitance to accommodate the LNA to operate in Blue-
tooth mode. The reuse of coils has an advantage because in that way
the chip area is saved and the need to design the second integrated
coil is avoided. The multi-band LNA for DECT and Bluetooth is
depicted in Fig. 3.
Vdc2
C1
C2
Lg
M3
Vrf
M1
M2
Ls
Vdc1’
Bluetooth
Vdc1
DECT
DECT Bluetooth
1.8 V 0 V
Rd
Vout
Vdd
Figure 3. Multi-band LNA for DECT and Bluetooth
Transistor M3 operates as a switch. When it conducts, it operates
in the triode region. In order to reduce the resistance of M3 when it
conducts and its contribution to the noise factor, M3 is made large
(W/L = 100/0.18) and the highest voltage equal to the voltage sup-
ply is applied on its gate. The values of capacitors C1and C2must
be calculated in order to satisfy matching conditions for DECT and
Bluetooth. It is necessary to take into account the capacitance of the
transistor M3when itdoes not conduct. Bythesimulations itwasde-
termined that CM3= 119 fF, which originates from the gate-source
and gate-drain overlap capacitances. Since the DECT operating fre-
quency (fdect= 1.9 GHz) is lower than the Bluetooth operating fre-
quency (fbt= 2.4 GHz), from (8) it can be calculated that:
gm,dect= gm,bt(
fbt
fdect
)2
(21)
This means that gm,dectis higher than gm,bt. As a consequence
Cgst,dectis greater than Cgst,bt(see 9). The same relation is valid for
the external capacitances: Cgsext,dect>Cgsext,bt. Hence, the transistor
M3 will be switched off in the Bluetooth mode and switched on in
the DECT mode. The capacitancesC1andC2can be calculated from
the equations (22) and (23).
C1+C2=Cgsext,dect
(22)
C1+
C2CM3
C2+CM3
=Cgsext,bt
(23)
Usingthesamedesign parameters: I =8mA, (W/L)M1=200/0.18,
Vdc1 = 700 mV, gm,dect= 70 ms, nopt= 14, Lg= 8 nH, Ls=
0.57 nH and Cgsext= 462 fF a rather low NFminof 1.3 dB is ob-
tained. The problem is Lg, which can not be implemented as a
bond-wire.Taking into account the package size and the die position
in the package, the inductance of 3 nH is for example more easily re-
alized as a bond-wire. Using (20) with Lgbond=3 nH, Lgopt=8 nH
and nopt= 14, the new value of parameter n (nbond) is obtained:
nbond= 2.5. Repeating the design procedure with nbond= 2.5 the
following design parameters are obtained: Lg= 3 nH, Ls= 1.2 nH
and Cgsext,dect= 1332 fF. With these design parameters a NFdectof
2 dB is simulated,which is for 0.7 dB higher than NFmin. This is the
cost that is paid for the full integration.
Using (21) with gm,dect= 70 ms, the new transconductance of the
transistor M1 that allows operation in Bluetooth mode is obtained:
gm,bt= 44 ms. It is achieved using the biasing voltage (Vdc1?) of
600 mV. In order to keep the same inductances and the same aspect
ratio of M1, a new value forCgsextmust be calculated. From (9), it is
obtained: Cgsext,bt= 703 fF. Finally, using (22) and (23), the values
for capacitances C1and C2, which allows multi-band operation are
calculated: C1= 600 fF and C2= 731 fF. They are implemented
as MIM capacitors and due to their very high quality factor their
contribution to NF is neglected.
Taking into account QLg= 10 and QLs= 5, the simulations results
presented in Table 1 are obtained.Comparing the simulated NF
Table 1. Simulation results for DECT/Bluetooth (BT) multi-
band LNA
NF (dB)
2.25
2.2
G (dB)
17
15
IIP3 (dBm)
0.5
3
S11dB
-16
-14
I (mA)
8
4
DECT
BT
of the multi-band LNA in DECT mode with NFdectof 2 dB when
LNA works only for DECT, the NF deterioration due to M3 is only
0.25 dB. Besides that, the LNA uses half power when it operates in
the Bluetooth mode. In this way the third design goal, multi-band
operation, is achieved.
6. CONCLUSIONS
An approach for the design of a multi-band LNA, yielding full inte-
gration and minimum noise figure is presented. Using this approach
the LNA for DECT and Bluetooth is designed and its feasibility is
proven. The NF degradation due to the multi-band operation, com-
pared with single-band LNA for DECT, is only 0.25 dB. A full de-
sign procedure that allows to determine all the LNA design parame-
ters is given. Applying this design procedure it is possible to achieve
a minimal noise figure and to make the trade off between a full in-
tegration and a minimal noise figure. The advantages of presented
design procedure over other design methodologies are discussed.
Acknowledgments
The authors thank the Technology Foundation STW for the financial
support.
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