Conference Paper

System design issues for 3D system-in-package (SiP)

Inst. of Electron., Tampere Univ. of Technol., Finland
DOI: 10.1109/ECTC.2004.1319401 In proceeding of: Electronic Components and Technology Conference, 2004. Proceedings. 54th, Volume: 1
Source: IEEE Xplore

ABSTRACT Development in electronics is driven by device and market needs. This paper focuses on system design issues for three-dimensional packaging technology and discusses interconnection density, material compatibility, thermal management, electrical requirements, related to delay and noise. Microelectronics packaging has to provide all future devices, such as electronics, actuators, sensors, antennas, optical/photonic, MEMS, and biological solutions. However, a 3D package is a cost effective solution to save placement and routing area on board using several IC processes in the same module. System-in-package (SiP) can combine all the electronic requirements of a functional system or a subsystem in one package. The driving force is integration without compromising individual chip technologies. In this work, a stacked system-in-package structure has been studied. The thermo-mechanical behavior of packages has been analyzed by finite element analysis (FEA) and the correlation between the experimental test results and the modeling was analyzed. A stacked 3D package can contain multiple heat sources that produce high power density. Therefore, thermal management needs extra attention to ensure safe operating temperatures under all conditions. The thermal behavior of the package was modeled using FEA and a boundary condition independent (BCI) compact thermal model (CTM) was built based on simulation results. In addition, high-speed signal and interfering environment set quite stringent requirements for 3D devices. Crosstalk between vertical connections was simulated and measured. Measurements of S-parameters were done using a network analyzer. The frequency range was 45 MHz to 20 GHz.

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