System design issues for 3D system-in-package (SiP)
ABSTRACT Development in electronics is driven by device and market needs. This paper focuses on system design issues for three-dimensional packaging technology and discusses interconnection density, material compatibility, thermal management, electrical requirements, related to delay and noise. Microelectronics packaging has to provide all future devices, such as electronics, actuators, sensors, antennas, optical/photonic, MEMS, and biological solutions. However, a 3D package is a cost effective solution to save placement and routing area on board using several IC processes in the same module. System-in-package (SiP) can combine all the electronic requirements of a functional system or a subsystem in one package. The driving force is integration without compromising individual chip technologies. In this work, a stacked system-in-package structure has been studied. The thermo-mechanical behavior of packages has been analyzed by finite element analysis (FEA) and the correlation between the experimental test results and the modeling was analyzed. A stacked 3D package can contain multiple heat sources that produce high power density. Therefore, thermal management needs extra attention to ensure safe operating temperatures under all conditions. The thermal behavior of the package was modeled using FEA and a boundary condition independent (BCI) compact thermal model (CTM) was built based on simulation results. In addition, high-speed signal and interfering environment set quite stringent requirements for 3D devices. Crosstalk between vertical connections was simulated and measured. Measurements of S-parameters were done using a network analyzer. The frequency range was 45 MHz to 20 GHz.
Conference Proceeding: A long-term reliability of adhesive flip chip joints using very thin chips[show abstract] [hide abstract]
ABSTRACT: Anisotropic conductive adhesives were used to attach daisy chained test chips on FR-4 test board. The area of the test chips was 5 mm×5 mm and the pitch was 250 μm. Half of the test chips were thinned to the thickness of 50 μm. Both test chip types had exactly the same test layout with peripherally situated gold bumps. Contact resistance measurements were performed using four-point and daisy chain methods. The reliability of the joints was studied by subjecting the specimens to temperature cycling and humidity tests. In addition, some of the test samples were subjected to a reflow treatment. Finally, the structure of the joints was studied with scanning electron microscopy. After 1000 cycles of the temperature cycling test both chip types showed good results. The average contact resistance of the joints had decreased, but a couple of open circuits had formed. Humidity tests caused some increase in contact resistance value. Reflow treatment did not cause significant degradation in jointsPolymers and Adhesives in Microelectronics and Photonics, 2001. First International IEEE Conference on; 02/2001
Conference Proceeding: Thru-silicon interconnect technology[show abstract] [hide abstract]
ABSTRACT: Wafer-level packaging (WLP) is forecast to be less expensive than die-level packaging, though many fundamentally new technologies are needed to fulfil this potential. For a complete WLP process flow to be cost-effective, all newly developed technologies should be simple and inexpensive to implement in high-volume manufacturing. Chip-scale packages (CSPs) produced with a WLP process flow are particularly advantageous when combined with flip-chip/BGA connections, since direct-chip attach (DCA) parts can thus be produced entirely by a wafer-fab. A new process technology-atmospheric downstream plasma (ADP) gas etching-allows for the WLP formation of backside thru-silicon contacts for DCA applications. Thru-silicon designs and manufacturing process flows are introduced as means to produce 3D wafer level packaging solutions. Standard silicon IC manufacturing unit-processes must be combined into robust process-flows to allow for the rapid deployment of wafer-level packaging throughout the industryElectronics Manufacturing Technology Symposium, 2000. Twenty-Sixth IEEE/CPMT International; 02/2000
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ABSTRACT: The accurate prediction of the temperatures of critical electronic parts at the package, board and system level is seriously hampered by the lack of reliable, standardized input data that characterize the thermal behaviour of these parts. The recently completed collaborative European project DELPHI has been concerned with the creation and experimental validation of thermal models (both detailed and compact) of a range of electronic parts, including mono-chip packages, heat sinks, electrolytic capacitors, transformers, and interfacing materials. The ultimate goal of the DELPHI project was to get component manufacturers to supply validated thermal models of their parts to end users by adopting the experimental techniques used to validate the detailed thermal conduction models of the parts, and the methods to generate compact models. Part II of this paper contains technical information on both experimental and numerical methods. In order to reduce design-cycle time and physical prototyping, equipment manufacturers need to ascertain the thermal performance of new systems at the earliest possible stage of the design process. Accurate, validated thermal models of the critical parts used in the design are needed to provide the thermal precision necessary to design out the functional and reliability failures that result from component overheatingIEEE Transactions on Components Packaging and Manufacturing Technology Part A 01/1998;