System design issues for 3D system-in-package (SiP)
ABSTRACT Development in electronics is driven by device and market needs. This paper focuses on system design issues for three-dimensional packaging technology and discusses interconnection density, material compatibility, thermal management, electrical requirements, related to delay and noise. Microelectronics packaging has to provide all future devices, such as electronics, actuators, sensors, antennas, optical/photonic, MEMS, and biological solutions. However, a 3D package is a cost effective solution to save placement and routing area on board using several IC processes in the same module. System-in-package (SiP) can combine all the electronic requirements of a functional system or a subsystem in one package. The driving force is integration without compromising individual chip technologies. In this work, a stacked system-in-package structure has been studied. The thermo-mechanical behavior of packages has been analyzed by finite element analysis (FEA) and the correlation between the experimental test results and the modeling was analyzed. A stacked 3D package can contain multiple heat sources that produce high power density. Therefore, thermal management needs extra attention to ensure safe operating temperatures under all conditions. The thermal behavior of the package was modeled using FEA and a boundary condition independent (BCI) compact thermal model (CTM) was built based on simulation results. In addition, high-speed signal and interfering environment set quite stringent requirements for 3D devices. Crosstalk between vertical connections was simulated and measured. Measurements of S-parameters were done using a network analyzer. The frequency range was 45 MHz to 20 GHz.
Conference Paper: Underfill characterization for multi-layer 3D-SiP stacked chip package[Show abstract] [Hide abstract]
ABSTRACT: In this paper, evaluation of underfill materials for 3D SiP packages where micro bump interconnections and solder bumps has been presented. Characterization of underfill materials was carried out in terms of adhesion testing on various chip passivation surfaces and process optimization for void free filling. Capillary underfill materials have been evaluated for micro bump interconnections for 3D stacked module with different size chips as well as 3D stacked module with same size chips, and moldable underfill has been evaluated for over molding of stacked module along with underfilling of solder bump interconnections. Die shear test was carried out on adhesion test samples and results revealed failure between chip and polyimide layers in polyimide samples, and mixed failure between underfill and passivation layer in SiN samples. Process optimization for void free underfilling for CUFs were carried out based on dispensing temperature, speed, length, pattern and effects of plasma treatments. For MUF, the transfer molding process optimization was carried out by varying transfer time and die temperature to achieve void free underfilling and molding process. CSAM and through scan analysis was carried out on the under filled samples to check the quality of the underfilling process. The optimized process results shown void free underfilling for both 3D stacked module packages with different size chips as well as same size chips.Electronics Packaging Technology Conference (EPTC), 2011 IEEE 13th; 01/2011
Conference Paper: Studies on reliability of a 3D system-in-package device[Show abstract] [Hide abstract]
ABSTRACT: To meet the needs of multifunction and miniaturization of modern electronic products, system-in-package (SiP) has been adapted as one of the most promising packaging technologies. It integrates different chips and devices into one package, which greatly reduces the package size and enhances the performance. However, the relatively complex structure of SiP may cause unexpected failure to the solder joints or silicon chips. In this paper, a 3D package with one larger chip on an FR4 board and four smaller chips on the back side was designed to study the reliability of SiP. The chips were flip-chip bonded to the FR4 board and experienced a set of reliability tests including thermal shock and drop test under JEDEC standards. Moreover, underfill was applied to enhance the reliability of the SiP. The effect of the multiple reflow processes for assembling the complex 3D sample on the reliability of SiP was examined. Failure analysis was carried out to find out the failure mechanism.2013 14th International Conference on Electronic Packaging Technology (ICEPT); 08/2013
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ABSTRACT: Publisher’s description: This book contains extended and revised versions of the best papers presented at the 16th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2008, held in Rhodes Island, Greece, in October 2008. The 14 papers presented together with an invited contribution were carefully selected from 56 papers. The papers cover a wide variety of excellence in VLSI technology and advanced research in the fields of VLSI/ULSI systems, embedded systems, and microelectronic design and test. The articles of this volume will not be reviewed individually.