Measurements of effective thermal conductivity for advanced interconnect structures with various composite low-k dielectrics
ABSTRACT Accurate specification of design groundrules for interconnect systems requires knowledge of the thermal behavior of the systems. A key parameter that characterizes the thermal behavior is the thermal conductivity of the inter-level dielectric (ILD). In practical VLSI applications, the metal interconnects are fully embedded in a stacked, composite ILD media, which presents difficult challenges for the accurate determination of thermal conductivity. In this paper, we propose the concept of an "effective thermal conductivity" to model such complicated, composite media, and introduce a simple methodology to accurately measure effective and bulk thermal conductivities of various thin dielectric layers in integrated circuits. We present measured effective conductivities of several composite media, including various Cu/low-k dielectric configurations such as Cu/SiCOH, Cu/SiLK®, Cu/fluorinated silicate glass (FSG), and a hybrid stack with Cu lines in SiLK® and Cu vias in un-doped silicate glass (USG). Measurements were recorded in the temperature range from 30°C to 120°C using a unique combination of fully embedded Cu lines as heater/thermometers, wafer-level temperature vs. power (TVP) measurements, and the Harmon-Gill (H-G) quasi-analytical heat conduction model. The thermal conductivities of all the films studied here were observed to increase with rising substrate temperature.
Conference Paper: Measurement of back end of line thermal resistance for 3D chip stacks[Show abstract] [Hide abstract]
ABSTRACT: The thermal resistances of thirty-nine different back end of line (BEOL) test sites consisting of four line levels and three via levels in SiCOH were measured. The measured unit resistance values ranged from 0.5 to 5.5 C-mm2/W. The percent via area was varied from 0.31 to 6.25 %, the percent line area from 17 to 67%, the configuration of the vias, the distance between vias, and the line and via pitch were also varied. The measured values were compared to results from an internally developed electromagnetic simulation tool, ChipJoule. Comparison of the simulations with measured values validated the ChipJoule tool, which can be used to simulate full BEOL structures using mask design data.Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM), 2013 29th Annual IEEE; 01/2013
Conference Paper: TACO: temperature aware clock-tree optimization[Show abstract] [Hide abstract]
ABSTRACT: In this paper, an efficient linear time algorithm TACO is proposed for the first time to minimize the worst case clock skew in the presence of on-chip thermal variation. TACO, while tries to minimize the worst case clock skew, also attempts to minimize the clock tree wirelength by building up merging diamonds in a bottom-up manner. As an output, TACO provides balanced merging points and the modified clock routing paths to minimize the worst case clock skew under thermal variation. Experimental results on a set of standard benchmarks show 50-70% skew reduction with less than 0.6% wirelength overhead.Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on; 12/2005
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ABSTRACT: In this study, intuitive is given on time-dependent thermal characteristics in multilevel interconnects subjected to carry either DC or pulsed-DC. FEM simulation is employed to model the propensity of temperature profile with respect to the variety of interconnects having different geometrical features in terms of metal width, metal height and distance between metal and Si substrate. Accordingly, a practical model that enables to prognosis temperature increase resulting from current-driven metal interconnects and temperature decrease after current carried along metal line stops is developed. It is found that a proposed model precisely predicts thermal transient arisen from metal interconnect, regardless of geometrical factors of metal dimension and location. In addition, transient thermal behavior of metal interconnects carrying pulsed DC with various frequencies is investigated. A circuit designer is required to adjust the maximum allowable current carried along metal interconnects according to the frequency of pulsed DC as well as geometrical dimensions of metal interconnects. Hence, robustness in circuit design even in the earlier stage of development phase can be accomplished for metal interconnects by suppressing electromigration and rupture caused by thermal transient.01/2011;