Measurements of effective thermal conductivity for advanced interconnect structures with various composite low-K dielectrics
ABSTRACT Accurate specification of design groundrules for interconnect systems requires knowledge of the thermal behavior of the systems. A key parameter that characterizes the thermal behavior is the thermal conductivity of the inter-level dielectric (ILD). In practical VLSI applications, the metal interconnects are fully embedded in a stacked, composite ILD media, which presents difficult challenges for the accurate determination of thermal conductivity. In this paper, we propose the concept of an "effective thermal conductivity" to model such complicated, composite media, and introduce a simple methodology to accurately measure effective and bulk thermal conductivities of various thin dielectric layers in integrated circuits. We present measured effective conductivities of several composite media, including various Cu/low-k dielectric configurations such as Cu/SiCOH, Cu/SiLK®, Cu/fluorinated silicate glass (FSG), and a hybrid stack with Cu lines in SiLK® and Cu vias in un-doped silicate glass (USG). Measurements were recorded in the temperature range from 30°C to 120°C using a unique combination of fully embedded Cu lines as heater/thermometers, wafer-level temperature vs. power (TVP) measurements, and the Harmon-Gill (H-G) quasi-analytical heat conduction model. The thermal conductivities of all the films studied here were observed to increase with rising substrate temperature.
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ABSTRACT: Three-dimensional (3D) chip stacks are receiving more attention for system performance enhancements. However, because of the higher circuit density, the cooling of 3D chip stacks gets more challenging. In conventional cooling methods, a heat sink or a micro-channel cooler is located at the top of the chip to dissipate the generated heat in a chip. In this paper, possible cooling methods from the bottom of a silicon interposer and cooling from the peripheral of a silicon interposer were proposed and evaluated. Based on the experimentally obtained thermal resistance of lead-free (SnAg) interconnections, the cooling performances of the above two cooling solutions were investigated by modeling and the requirements were clarified.Semiconductor Thermal Measurement and Management Symposium, 2010. SEMI-THERM 2010. 26th Annual IEEE; 03/2010
Conference Paper: Enabling SPICE-type modeling of the thermal properties of 3D-stacked ICs[Show abstract] [Hide abstract]
ABSTRACT: Technologies enabling 3D-stacking of chips with through-Si interconnects are becoming of increased interest. These 3D-stacking technologies result in strongly reduced system dimension and hence a significant increase of power density. The capacity of the system to efficiently transport and dissipate heat is of major importance to assure functionality and reliability of the system. This paper reports on the thermal resistance modeling of 3D-die stacks, that are built according to IMECs 3D-SIC (3D-Stacked IC) process flow. The main result of this work is a semi-analytical parametric thermal resistance model that may be used to estimate the thermal resistance of any given 3D-SIC geometry by solving a thermal resistance network (SPICE-type simulation)Electronics Packaging Technology Conference, 2006. EPTC '06. 8th; 01/2007
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ABSTRACT: When measuring the best linear approximation of systems suffering from nonlinear distortions a specific class of periodic multiharmonic signals is normally used. These are signals with uniformly distributed random phases, termed random phase multisines. In this paper, it is shown that measurements of the best linear approximation of nonlinear systems can also be obtained by using a special type of low crest factor multisines. These signals are compared to random phase multisines and their properties are analysed in detail.Instrumentation and Measurement Technology Conference, 2002. IMTC/2002. Proceedings of the 19th IEEE; 02/2002