Page 1
Novel Modulation Schemes Minimizing the Switching Losses of Sparse Matrix Converters
Johann W. Kolar and Frank Schafmeister
ETH Zurich, Power Electronic Systems Laboratory
ETH Zentrum / ETL H22, Physikstr. 3, CH8092 Zurich/SWITZERLAND
Tel.: +411632 2834 Fax.: +411632 1212
email: kolar@lem.ee.ethz.ch
Abstract. The switching losses of a threephase Sparse Matrix Converter
(SMC) operating in the lower modulation range are minimized by
employing the lowest and the second largest input linetoline voltage for
the formation of the converter DC link voltage. The resulting current
stresses on the power semiconductors and the switching frequency ripple
RMS values of the filter capacitor voltages and output currents are
calculated by digital simulation and compared to conventional modulation.
Finally, a modulation scheme is introduced which allows the generation of
reactive input power also for missing active power transfer via the DC link
and/or purely reactive load. This is a basic requirement for operating the
SMC in boost mode where the output filter capacitor voltages have to be
controlled sinusoidally also for noload operation.
1 Introduction
Sparse Matrix Converter (SMC, cf. Fig.1) systems [1] are
functionally equivalent to Conventional Matrix Converters (CMC)
but are characterized by a lower realization effort and a lower
control complexity and are therefore especially interesting for an
industrial application.
p
Spa
Dap
a
b
c
A
B
C
ia
i
iA
n
u
Sa
Dpna
SpA
DAp
Fig.1: Topology of the Sparse Matrix Converter (SMC) according to [1].
Within each pulse half period two linetoline voltages are
switched into the DC link of the SMC by proper control of the input
stage (cf. Fig.2). There, the input stage commutation is at zero
current (cf. i in Fig.2, Fig.6 in [1], [2]) what allows to avoid a
multistep commutation scheme in dependency on the sign of the
commutating voltage or commutating current as required for the
CMC and/or results in low switching losses and high converter
reliability.
For employing the largest and the second largest positive
linetoline voltage for the formation of the DC link voltage a
maximum output voltage range is achieved, however, relatively
large switching losses of the output stage do occur. The basic
properties of this modulation scheme, which will be denoted as
modulation scheme I in the following are shown in Fig.2. For low
output voltage amplitude therefore a modification of the modulation
scheme has to be considered which reduces the output stage
switching losses by switching linetoline input voltages of low
instantaneous value into the DC link.
In this paper a novel SMC modulation scheme is
proposed (denoted as modulation scheme II) where within each
pulse half period subsequently the lowest positive and the second
largest input linetoline are switched into the DC link. In
combination with the clamping of the SMC output stage bridge legs
within π/3wide interval in the vicinity of the maxima of the
corresponding output phase currents this results in minimum system
switching losses. In Section 2 the relative ontimes of the input and
output stage switching states are calculated and a concept for
shifting part of the output stage switching losses to the input stage is
described.
tµ = 0TP
2
0
+π/6
π/6
uac
uab
ubc
ua
u
ub
uc
uba
uca
ucb
1
TP
τac
}
τabτac
}}}
0
τab
u
i
+π/3
π/3
Fig.2: Modulation Scheme I (cf. Fig.9 in [1]); (a) time behavior of the
mains phase voltages, the mains linetoline voltages, the SMC DC link
voltage u and of the local average value of the DC link voltage and the DC
link current, ū and ī, within a 2π/3wide interval of the input period
(φ1=−π/3…+ π/3); (b) time behavior of u, i, the mains phase currents ii,
i=a,b,c, within a pulse period tµ=0…TP for φ1 in 0…+π/6 and φ2 in 0…+π/3
(φ2 denotes the phase of the reference value of the output voltage space
vector, cf. Eq.(14)); furthermore shown: switching functions of the rectifier
and the inverter stage (sapa=1 indicates a bidirectional connection of phase
input a and the positive DC link bus p, and/or the turnon state of Sa and Spa;
sA=1 denotes the turnon state of SpA and/or the turnoff state of SnA). For the
sake of clarity a low pulse frequency is assumed and the ripple components
of u and i are neglected.
sapa
sbpb
scpc
sana
sbnb
scnc
sA
sB
sC
TP
u
i
i
uac
uac
iA
iC
iC
iA
τ(100), ac
τ(110), ac
τ(111), ac
τ(111), ab
τ(110), ab
τ(100), ab
τ(100), ab
τ(110), ab
τ(111), ab
τ(111), ac
τ(110), ac
τ(100), ac
τac
τac
τab
τab
TP
1
2
tµ = 0
uab
1
0
ia
ia
ib
iA
iC
iC
iA
ic
ic
ib
iA
iC
u
iC
iA
iA
iC
(a)
(b)
= ϕ1
Page 2
In Section 3 the modulation schemes I and II are comparatively
evaluated based on the current stresses on the power
semiconductors and the RMS values of the ripple components of
the filter capacitor voltages and output currents. Finally, in Section
4 a modification of modulation scheme I is proposed which allows
the generation of reactive power at the converter input also for
purely reactive load, i.e. without transfer of active power via the
DC link.
2 Minimizing Switching Losses at Low Output Voltage
As shown in Fig.2 the commutation of the input stage is within the
freewheeling interval of the output stage, i.e. at zero DC link
current i=0. Therefore, switching losses do occur only for the
output stage and are determined by the instantaneous value of the
DC link current i and the DC link voltage u.
The DC link current i is directly defined by the output
current phase displacement Φ2 for a given ϕ2. Therefore, the only
possibility for minimizing the switching losses is to employ
sections of the input linetoline voltage with minimum
instantaneous value for the formation of the DC link voltage.
uab
0
+π/3
π/3
uac
ubc
u
}}}}
ua
ub
uc
uba
uca
ucb
tµ = 0TP
1
2
TP
τabτbc
τab
τbc
0
u
i
+π/6π/6
sapa
sbpb
scpc
sana
sbnb
scnc
sA
sB
sC
TP
u
u
i
i
uab
uab
iA
iC
iC
iA
τ(100), ab
τ(110), ab
τ(111), ab
τ(111), bc
τ(110), bc
τ(100), bc
τ(100), bc
τ(110), bc
τ(111), bc
τ(111), ab
τ(110), ab
τ(100), ab
τab
τab
τbc
τbc
TP
1
2
tµ = 0
ubc
1
0
iC
iA
ia
ia
iA
iA
iC
iC
ib
ib
iA
iC
iC
iA
ic
ic
iC
iA
Fig.3: Proposed modulation scheme (modulation scheme II); representation
of the voltages, currents and switching functions as for modulation scheme I
in Fig.2. In contrast to modulation scheme I the input stage bridge leg a is
switching with pulse frequency between the positive and negative DC link
bus. As the commutation of the input stage is at zero DC link current this
however does not result in switching losses.
There, the combination of the input phases has to be selected such
that the distribution of the DC link current i to the input phases
results in phase currents being proportional to the corresponding
phase voltages, i.e. ia,b,c ~ ua,b,c (cf. Eq.(6)). The resulting modulation
scheme which is denoted as modulation scheme II in the following
is shown in Fig.3.
In analogy to Section IV in [1] the calculation of the
relative ontimes of the power transistors of the input stage can be
limited to a π/6wide interval, φ1=0…π/6, of the mains period.
Based on this the turnon times for further intervals can be derived
by symmetry considerations.
Assuming a constant local average value ī of the DC link
current i for each rectifier switching state of a pulse half period
(time intervals τab and τbc, cf. Eq.(24) in [1]) we have for the local
average values of the input phase currents
idi
ab
iddi
ab bcb
)(
−=
Under consideration of
1
=+
bcab
dd
Eq.(1) can be rewritten as
idi
abb
)21 ( −=
and/or
i
d
⋅+
2
For ohmic fundamental mains behavior of the SMC input stage,
°=φ
0
1
,
and/or
ui ~
bb
ui ~
cc
ui ~
Eq.(4) results in
u
uu
+
2
a=
idi
bcc
−=
. (1)
(2)
(3)
ab
a
ab
ii
=
. (4)
(5)
aa
(6)
ac
a
ab
a
ab
u
u
d
==
(7)
where a symmetric sinusoidal input phase voltage system
)cos(
ˆ
11
π−ω=
tUu
c
is assumed. Furthermore, Eqs.(1), (2) and (6) yield
u
ii
⋅+
2
) 3/2cos(
ˆ
) 3/2cos(
ˆ
11
11
π+ω=
ω=
tUu
tUu
b
a
. (8)
ac
c
ab
c
bc
u
i
d
−=
−
=
. (9)
The timedependent local average value of the DC link voltage (cf.
Fig.3) now results as
3
ˆ
2
u
ac
)
6
cos(
1
ˆ
2
3
1
1
2
1
π
−ω
==+=
t
U
U
ududu
bcbcabab
. (10)
With reference to Eq.(10) the modulation limit, i.e. the maximum
value of the amplitude of the output phase voltage fundamental is
1
3
and/or in comparison to modulation scheme I
ˆ
58. 0
ˆ
3
Due to the time dependency of ū the formation of a constant
amplitude Û2 of the output phase voltages requires a variation of the
SMC output stage modulation index
16/1min
,
max, 2
ˆ
2
1

3
1
ˆ
UuuU
II
===
π=ϕ
(11)
IIII
UUU
max, , 2max,, 2max,, 2
1
ˆ
≈=
.
(12)
= ϕ1
Page 3
) 6/cos(
ˆ
ˆ
3
4
ˆ
1
1
2
2
1
2
u
2
π−ω==
t
U
UU
m
. (13)
There, we have for the absolute turnon times of the active
switching states
ˆ
2
),100(
+ϕ=τ
aab
u
U
)cos()(
ˆ
ˆ
3
) sin()(
ˆ
ˆ
3
) sin(
ˆ
ˆ
3
)cos(
ˆ
3
6
2
2
1
2
),100(
2
2
1
2
),110 (
2
2
1
2
),110(
6
2
2
1
π
π
+ϕ−=τ
ϕ−=τ
ϕ=τ
c
p
bc
c
p
bc
a
p
ab
p
u
U
U
T
u
U
U
T
u
U
U
T
U
T
(14)
where φ2 denotes the phase of the output voltage space vector u2*
(u2*=Û2, cf. Fig.10 in [1]) which has to be formed in the average
over a pulse half period (for Eq.(14) φ2=0…π/3 and φ1=0… π/6 is
assumed).
In the following the voltage transfer ratio of the SMC shall be
characterized using
ˆ
ˆ
U
U
I
1
2
3
2
max, , 2
2
12
ˆ
ˆ
UU
M
==
. (15)
Besides the DC link voltage the switched current takes direct
influence on the output stage switching losses. Therefore, according
to [3] an output stage bridge leg is advantageously not switched in
the vicinity of the maxima of the related phase current; the phase
output then remains clamped to the positive and/or negative DC
link bus within a π/3wide interval of the positive and the negative
output half period. For Φ2=0 a symmetric clamping around the
maximum of the output phase voltage fundamental (cf. Fig.4(b) and
(c)) results in minimum switching losses. For increasing current
phase displacement Φ2 the clamping interval has to be shifted
accordingly, but has to remain within an angle interval of ±π/3
relative to the phase voltage maximum. Therefore, for Φ2>π/6
higher output switching losses as for Φ2=0 will occur (cf.
Figs.5(c),(d) and (g),(h)). For an optimal positioning of the
clamping interval the time behavior of the phase current and
(contrary to inverter systems with constant DC link voltage as
considered in [3]) the time dependency of the envelopes of the
input linetoline voltages which are employed in each pulse half
period for DC link voltage formation would have to be considered.
Fig.4:…………
Fig.4: Modulation of the SMC input and output stage for modulation scheme I (cf. (a)(d)) and modulation scheme II (cf. (e)(h)) for different values of
the output current phase displacement Φ2=0 (b),(f); Φ2=π/4 (c),(g); Φ2= π/2 (d),(h). Representation of the potential of the positive and negative DC link
bus, up and un, with reference to the mains star point (cf. (a) and (e)) and of the switching functions sapa and sana (cf. Fig.2 and Fig.3) of input stage bridge
leg a; furthermore shown: voltage, current and switching function of power transistor SpA of the SMC output stage. The positioning of the clamping
intervals of SpA is under consideration of a minimization of the transistor switching losses.
Remark: For changing the input stage switching state within the
freewheeling interval of the output stage (cf. Fig.2(b) and Fig.3(b))
for modulation scheme I and II switching losses are limited to the
output stage. A partitioning of the switching losses between input
and output stage is possible for positive DC link current i>0. There,
by turning off an input stage power transistor, e.g. Sbnb in Fig.5, the
output stage is forced from an active switching state into (passive)
freewheeling operation and the turnoff losses are taken over by
Sbnb. At the end of the freewheeling interval the subsequent lineto
line input voltage is applied to the DC link by turning on Scnc (cf.
Fig.5) and the output stage returns into the prior active switching
state where again no output stage switching losses do occur. A
detailed description of this control concept will be given in a future
paper.
uac
uab
sapa
sbnb
scnc
spA
spB
spC
i
i
τ(100), ac
τ(110), ac
τ(110), ab
τ(110), FW
τ(100), ab
TP
1
2
tµ = 0
1
0
u
iA
iC
iA
iC
0
0
3 Comparative Evaluation of Modulation Schemes I and
II
The results of a simulation of the stationary operating behavior of a
SMC employing the proposed modulation scheme II are compiled
in Fig.6 for
mains frequency f1=50Hz
output frequency f2=100Hz
switching frequency fP=25kHz
load inductance L=1mH
input filter capacitance C=9µF (star connection).
In order to determine the switching frequency ripple of the filter
capacitor voltages independent of the inner mains impedance
up
un
sapa
sana
0
20ms
5ms
10ms
15ms
uSpA
iSpA
spA
0
20ms
5ms
10ms
15ms
(f)
uSpA
iSpA
spA
0
20ms
5ms
10ms
15ms
(g)
uSpA
iSpA
spA
0
20ms
5ms
10ms
15ms
up
un
sapa
sana
0
20ms
5ms
10ms
15ms
uSpA
iSpA
spA
0
20ms
5ms
10ms
15ms
uSpA
iSpA
spA
0
20ms
5ms
10ms
15ms
uSpA
iSpA
spA
0
20ms
5ms
10ms
15ms
Fig.5: Commutation of the SMC output
stage into a passive freewheeling state
(freewheeling action despite the active
switching state control signals remain
applied to the output stage power
transistors) by turning off a power
transistor (Sbnb) of the input stage for
positive DC link current i>0. For
conventional modulation (cf. Fig.2), the
commutation of the input stage is at
zero current and/or switching losses
only do occur for the output stage.
(b)
(c)
(a)
(e)
(d)
(h)
Page 4
and/or the dimensioning of an input filter the system is fed by a
purely sinusoidal current. There, the current phase displacement
and amplitude is adjusted such that a filter capacitor voltage
fundamental amplitude of Û1= 327V (equivalent to U1,RMS= 230V)
is achieved. Furthermore, a load voltage is impressed at the output
side which ensures a load current fundamental amplitude of
Î2=17.75A independent of the selected current phase displacement
Φ2; for M12=1 and Φ2=0 this is equivalent to PO=7.5kW. The
clamping intervals of the output stage bridge legs are shifted with
increasing output current phase displacement Φ2 as shown in Fig.5
in order to always achieve a maximum reduction of the output stage
switching losses.
As shown in Figs.6(a),(b) and Fig.7 the proposed
modulation scheme II reduces the average DC link voltage and
therefore the output stage switching losses by a factor of about two
as compared to modulation scheme I.
However, for the formation of an output voltage of equal
amplitude Û2 a higher modulation index of the output stage is
required as for modulation scheme I. This results in a larger width
of the sections of the output currents forming the DC link current
and/or in higher conduction losses of the input stage (cf. Fig.8 and
Fig.9) and in a higher ripple ∆u1 of the input filter capacitor
voltages and/or a higher RMS value IC,RMS of the filter capacitor
current (cf. Fig.6(f) and Fig.10(a) and Fig.11(a)). Furthermore,
∆U1,RMS and IC,RMS are increased by the occurrence of current
pulses of equal magnitude but opposite sign in the vicinity of the
input current zero crossings (cf. ib in Fig.3(b) und ia in Fig.6(e)).
As shown in Figs.6(c) and (f) and Fig.10(b), modulation schemes I
and II result in an approximately equal RMS value ∆I2,RMS of the
output current ripple for given voltage transfer ratio M12. This is
again caused by the larger ontime of the active switching states of
the output stage and/or by the larger width of the output voltage
pulses of modulation scheme II which lead to an equal change of
the output phase currents as the voltage pulses of smaller width but
higher amplitude occurring for modulation scheme I.
An advantage of modulation scheme II over scheme I is
the lower value of the switched voltage which results in a lower
amplitude of the common mode component of the output voltage
and/or in lower conducted electromagnetic emissions of the
converter system (Fig.11(b)).
00.20.40.60.81
M12
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
PSw,r
I
II
φ2=π/4
φ2=0
φ2=π/4
φ2=0
Fig.7: Normalized switching losses PSw,r of a transistor of the output stage
(e.g. of SpA). Assuming a linear dependency of the transistor switching losses
on the switched voltage and current, for determining PSw,r the sum of the
transistor voltage and current products at the turnon and turnoff instants is
calculated over the least common multiple Tm of the mains and output
period, ΣTmiSpAuSpA/(4/3Û1Î2Tm/TP). The normalization to 4/3Û1Î2Tm/TP
(TP=1/fP) results in a quantity being independent of the absolute value of the
switched voltage and current and the considered time period. The factor 4/3
considers that there are in total 8 switching actions of the output stage and/or
8/6 switching actions of a single output stage power transistor within a pulse
period TP.
16
φ2 = 0
00.20.40.60.81
M12
0
2
4
6
8
10
12
14
IS,AVG
[A]
iSa, I
iSa, I +
iSpA, I
iSa, II
iSa, II +
iSpA, II
Fig.8: Average values of the input stage transistor Sa and of the output stage
transistor SpA in dependency on the voltage transfer ratio M12 (cf. Eq.(15))
for Φ2=0. Spa does not conduct current for Φ2=0 and shows only a very low
current average value for Φ2=π/4 (cf. Fig.17 in [1]), therefore, iSpa is not
shown. Index I refers to modulation scheme I, index II to modulation
scheme II. Simulation parameters as for Fig.6, but f2=50Hz. Increasing M12
results in an increasing width of the output current sections forming the DC
link current and therefore in a linear increase of the input stage transistor
current average value. Increasing Φ2 results in lower instantaneous DC link
current values and accordingly in lower input stage conduction losses.
0
20ms
5ms
10ms
15ms
uA
uA
iA
u
u
0
20ms
5ms
10ms
15ms
i
i
ia
ia
ua
0
20ms
5ms
10ms
15ms
iA
ua
∆ua
∆iA
u
uA
uA
iA
u
0
Fig.6: Simulation of the SMC operating behavior for modulation scheme I (cf. (a)(c)) and modualtion scheme II (cf. (d)(f)); (a), (d) DC link voltage u, local
average value ū, output phase voltage uA (with reference to the inductive load star point), local average value ūA, output phase current iA; (b), (e) DC link
current i, local average value ī, input phase current ia, local average value īa, input phase voltage ua; (c), (f) input phase voltage ua, ripple component ∆ua, and
output phase current iA and ripple component ∆iA; scales: 200V/div, 15A/div (∆ua: 20V/div, ∆iA: 1.5A/div); M12=0.1, Φ2=0.
20ms
5ms
10ms
15ms
i
i
ia
ia
ua
0
20ms
5ms
10ms
15ms
ua
iA
∆ua
∆iA
0
20ms
5ms
10ms
15ms
(e)
(b)
(c)
(f)
(a)
(d)
Page 5
0 0.20.4 0.6 0.81
M12
0
2
4
6
8
10
12
14
16
ID,AVG
[A]
iDap, I
iDpna, I +
iDap, I
φ2 = 0
iDAp, I +
iDpna, I +
iDap, I
iDAp, II +
iDpna, II +
iDap, II
00.20.40.6 0.81
M12
0
2
4
6
8
10
12
14
16
ID,AVG
[A]
iDap, I
iDpna, I +
iDap, I
iDAp, I +
iDpna, I +
iDap, I
iDAp, II +
iDpna, II +
iDap, II
φ2 = π/4
Fig:9: Average values of the power diode currents of the input stage
(diodes Dap and Dpna) and of the output stage (diode DAp) in dependency on
the voltage transfer ratio M12 (cf. Eq.(15)) for Φ2=0 and Φ2=π/4. For details
of the representation and an explanation of the characteristic of the
dependency on M12 see caption of Fig.8.
1.6
0 0.20.4 0.6 0.8 1
M12
0
0.2
0.4
0.6
0.8
1
1.2
1.4
∆U1a,RMS,r
I, φ2 = 0
I, φ2 = π/4
II, φ2 = 0
II, φ2 = π/4
00.2 0.40.60.8 1
M12
0
0.1
0.2
0.3
0.4
0.5
0.6
∆I2A,RMS,r
I
II
φ2=π/4
φ2=π/4
φ2=0
φ2=0
Fig.10: Normalized RMS value of the input filter capacitor voltage ripple
and of the output current ripple, ∆U1a,RMS,r and ∆I2A,RMS,r, for Φ2=0 and
Φ2=π/4. normalization with reference to Û1TP/(8L) (cf. [3]) and/or
Î2TP/(8C). For details of the representation see caption of Fig.8.
As a closer analysis shows, the characteristics shown in Figs.711
which have been calculated assuming f1/f2=1 are also valid in good
approximation for a wide variation of the ratio f1/f2 of the input and
output frequency. This is proven by Fig.12 e.g. for ISa,AVG,
∆U1a,RMS,r and ∆I2A,RMS,r.
4 Conclusions
For achieving a low volume of the filter components a matrix
converter has to be operated at high switching frequency.
Therefore, the switching losses are in general constituting a large
share of the total converter losses.
The modulation scheme II proposed in this paper allows
to cut the switching losses of a SMC operating in the lower
modulation range in half as compared to conventional modulation I
for equal RMS value of the output current ripple. The converter
conduction losses are only slightly increased. Accordingly, the
thermal stress on the power semiconductors is considerably reduced
what permits an increase of the output current at low output fre
00.20.4 0.60.81
M12
0
5
10
15
20
IC,RMS
[A]
I, φ2 = 0
I, φ2 = π/4
II, φ2 = 0
II, φ2 = π/4
0 0.20.40.60.81
M12
0
50
100
150
200
250
300
U0,RMS
[V]
I
II
φ2=π/4
φ2=0
φ2=0
φ2=π/4
Fig.11: RMS values IC,RMS,r and U0,RMS,r of the filter capacitor current and of
the commonmode component of the SMC output voltage in dependency on
the voltage transfer ratio M12.
10
I
00.20.40.6 0.81
M12
0
1
2
3
4
5
6
7
8
9
ISa,AVG
[A]
φ2 = 0
φ2 = π/4
φ2 = π/2
I
00.20.40.60.81
M12
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
∆U1a,RMS,r
φ2 = 0
φ2 = π/4
φ2 = π/2
00.20.40.6 0.81
M12
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
I
φ2 = 0
∆I2A,RMS,r
Fig.12: Dependency of input stage transistor current average value ISa,AVG,r,
of the normalized RMS value of the input filter capacitor voltage ripple
∆U1a,RMS,r and of the normalized RMS value of the output current ripple
∆I2A,RMS,r on M12 for different values of the output frequency f2; ?: f2 =
500Hz, ●: f2 = 250Hz, ? ?: f2 = 100Hz, ○: f2 = 50Hz, ▲: f2 = 5Hz; f1=50Hz,
modulation scheme I, normalization as for Figs.8 and 10; remaining
parameters as for Fig.8. The integration required for the calculation of the
average and RMS values is performed over the least common multiple of the
input and output periods T1=1/f1 and T2=1/f2.
quency and/or of the torque of an AC drive at low speed. As a
disadvantage a higher ripple of the input filter capacitor voltages
has to be accepted.
Alternatively, the reduction of the switching losses can be utilized
for an increase of the switching frequency. This allows to maintain
Page 6
a filter capacitor voltage ripple given for conventional modulation I
and features a reduction of the RMS value of the output current
ripple by a factor of two.
In a next step the proposed modulation scheme II will be
experimentally verified for a 7.5kW prototype of the SMC. There it
is important to consider that a large ripple of the filter capacitor
voltages results in passive freewheeling operation in the vicinity of
u≈0 which causes a distortion of the output voltage formation.
Therefore, a compensation scheme based on output voltage
measurement has to be employed or the modulation has to be
changed over to modulation scheme I in order to ensure a high
output current quality.
i
p
A
B
C
a
b
c
iA
ia
n
u
uNA
Fig.13: Operation of a SMC in boost mode. The definition of the positive
voltage and current directions is assumed equal as for buckmode operation
in Fig.1.
uac
uac
iA
iC
iC
iA
τ(100), ac
τ(110), ac
τ(111), ac
τ(111), ab
τ(110), ab
τ(100), ab
τ(010), ab*
τ(111), ab*
τ(111), ac*
τ(101), ac*
τac
τac*
τab
τab*
TP
1
2
tµ = 0
uab
i
u
uAB
iB
iB
uac
iC
iA
ib
uab
uab
uac
iB
uac
iA
iC
iC
iA
τ(111), ac
τ(111), ab
τac
τab
TP
1
2
tµ = 0
uab
i
u
iB
τ(100), ac + Min(τ(110), ac ; τ(101), ac*)
τ(100), ab  τ(010), ab*
...if (τ(100), ab < τ(010), ab*)
...if (τ(100), ab > τ(010), ab*)
iB...if (τ(110), ac < τ(101), ac*)
...if
(τ(110), ac > τ(101), ac*)
τ(110), ac  τ(101), ac*
τ(110), ab + Min(τ(100), ab ; τ(010), ab*)
Fig.14: Proposed modulation scheme (a) for generating reactive output
current (filter capacitor current, cf. Fig.13) for zero active power transfer via
the DC link; the switching state sequence of a pulse period TP (cf. (a)) can
be combined in a half pulse period as shown in (b).
In the course of future research also the operation of the SMC in
boost mode (cf. Fig.13) which has not been treated in the literature
so far will be analyzed in detail. There, the main subject is the
generation of purely reactive output power at no load, i.e. without
active power flow via the DC link (Φ1= ±π/2 and Φ2= ±π/2). This
is not possible for modulation scheme I or II (cf. Section VB in [1])
as the DC link current shows zero local average value within each
turnon interval of a linetoline input voltage for Φ2= ±π/2;
Accordingly, no local average value of the filter capacitor current
can be formed.
The modification of the modulation concept required for
purely reactive power operation is shown in Fig.14(b) at the
example of modulation scheme I. There, the first half of a pulse half
period, tµ=0…TP/2, is utilized for voltage formation (as given for
conventional modulation). Within the second half of the pulse
period the filter capacitor currents (e.g. ib) are formed, where the
switching state turnon times (e.g. τ(010),ab* and τ(101),ac*) are
determined such that no local average value of the DC link power
p=u.i does result. There, the DC link current in general shows a
local average value (cf. Fig.15). The maximum value of the reactive
output current available for purely reactive power operation (Φ1=
±π/2 and Φ2= ±π/2) which, e.g. could be utilized for a sinusoidal
control of the output filter capacitor voltages at no (active) load is
shown in Fig.16. A detailed discussion and experimental
verification of the novel control concept will be given in a paper to
be published in near future.
u
u
0
20ms
5ms
10ms
15ms
uA
uA
iA
i
i
ia
ia
ua
0
Î1q,max
Î2
20ms
5ms
10ms
15ms
0.40.60.8 1.0 0.2
0.2
0.4
0.6
M12
= 1/2.(1  3/4 M12)
Î1q,max
Î2
References
[1] Kolar, J.W., Baumann, M., Schafmeister, F., and Ertl, H.: Novel
ThreePhase ACDCAC Sparse Matrix Converter, Part I and II.
Proceedings of the 17th Annual IEEE Applied Power Electronics
Conference, Dallas (Texas), USA, March 10  14, Vol. 2, pp. 777  791
(2002).
[2] Wei, L., and Lipo, T.A.: A Novel Matrix Converter Topology with
Simple Commutation. Record of the IEEE Industry Applications Society
Annual Meeting, Chicago, Sept. 30 – Oct. 4, Vol. 3, pp. 17491754 (2001).
[3] Kolar, J.W., Ertl, H., and Zach, F.C.: Influence of the Modulation
Method on the Conduction and Switching Losses of a PWM Converter
System. IEEE Transactions on Industry Applications, Vol. 27, No. 6, pp.
10631075 (1991).
Fig.15: Digital simulation
of the operating behavior
of the SMC in boost
mode for Φ1=π/2 and
Φ2=+π/2; modulation as
shown in
parameters as given in
Section 3;
200V/div, 20A/div.
Fig.14,
scales:
Fig.16: Dependency of
the normalized maximum
fundamental amplitude of
the reactive output phase
current, Î1q,max,r, on the
voltage transfer ratio M12
in case no active power is
transferred via the DC
link; modulation
shown in Fig.14.
as
(a)
(b)
Download fulltext