Hybrid multisite testing at manufacturing

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Hybrid Multisite Testing at Manufacturing
H. Hashempour, F.J. Meyer, F. Lombardi, and +F. Karimi
Northeastern University, Dept. of ECE, Boston Mass 02115
+LTX Corp., 3930 North First Street, San Jose, CA 95134
Email :
?hhashemp, fmeyer, lombardi
?@ece.neu.edu
ABSTRACT
This paper deals with Hybrid multisite testing of VLSI chips
by utilizing automatic test equipment (ATE) in connection
with built-in self-test (BIST).The performanceof a multisite
testing process is analyzed using device-under-test (DUT)
parameters (such as yield and average number of faults per
DUT) as well as test process features (such as number of
channels, coverage and touchdown time for the head). Two
scenarioswhichpermitimmediateanddelayedreplacements,
are considered and analytical models are given to establish
the multisite test time of an ATE. A hybrid BIST and ATE
approach is also analyzed to improve the performance of a
multisite test environment and to better utilize the channels
in the head of the tester.
1. Introduction
Sub-microntechnologyhas resultedinthe manufacturingof
complex chips; a one billion-transistor chip is envisioned in
the near future. Testing of these chips requires a departure
from traditional practice; Automatic Test Equipment (ATE)
is commonly used to apply test vectors to a device-under-
test (DUT), to analyze the outputs of the DUT, and identify
each DUT as either fault free or faulty [1] [2].
As an alternative to ATE, Built In Self Test (BIST) tech-
niques and schemes have been proposed [3] [4]. The ad-
vantages of BIST include enhanced test application time
[4], excellent tester-to-DUT bandwidth and efficient use of
tester memory. However the quality of BIST patterns is
low andmanyrandom-resilientfaults can notbe detectedby
BIST generated vectors. The use of deterministic patterns
through an ATE is a necessity when addressing the prob-
lems associated with testing devices with a low defect level
[2]. Recently, BIST and ATE have been analyzed in a sym-
biotic arrangement by which it is possible to have a com-
bined or hybrid scenario such that most advantagesof these
techniquescan be utilized[3] [5] [6] [7] [8]. Currently,ATE
systems are commercially available with up to 1024 chan-
nels [9] [10] [11] [12]. With test pin requirements ranging
from 32 (for RF) to 512 (for high performance ASIC and
Microprocessor) [13], it is possible to have a multisite pro-
cess by which multiple DUTs are tested at the same time.
During multisite testing, most of the resources in the
tester are shared among DUTs. Hence, when identified as
faulty, a DUT cannot be replaced from the head until the
test process of all DUTs has been completed. This results
in a waste of resources because ATE channels assigned to
DUTs which have already been identified as faulty, are left
idle during this period. The idle time is a function of the
yield (i.e. the probability of a chip to be fault free) and cov-
erage. This affects the expected number of faulty DUTs to
be tested in parallel because channel utilization in the pres-
ence of many faulty DUTs could be small. The idle time
is also a function of the times to establish either the failure
or the success of a DUT to pass the test. These times are
referred to as the fail and pass times of a DUT. Various test
schedulingtechniqueshavebeenproposedtochangethe ap-
plication order of the tests [14] [15]; in a multisite process,
this may result in a larger difference between pass and fail
times which increases the idle time and makes channel uti-
lization worse. Moreover, test engineers tend to write pro-
grams that detect the most probable faults first, thus often
resulting in a substantial difference between expected fail
and pass times.
In this paper, we present a detailed analysis of multisite
test time on a ATE which takes into account different man-
ufacturing parameters (such as yield, fail time, pass time,
number of DUTs, number of tester channels, and fault cov-
erage). We model the test process as a series of stages in
which different levels of fault coverage are achieved by uti-
lizingahybridarchitecture,i.e. BISTandATE.Closedform
expressions are introduced for evaluating multisite test time
and the relation between channel idle time and yield. We
then analyze a scheme for multisite testing and show its ef-
fectiveness in reducing tester time. The proposed multisite
test scheme is based on utilizing BIST for screening DUTs
prior to the multisite ATE process.
This paper is organized as follows: Section 2 presents
the preliminaries inclusive of problem definition. The prob-
lem characterization as related to multisite testing using an
ATEisaddressedinSection3. Section4analyzesthehybrid
ITC INTERNATIONAL TEST CONFERENCE Paper 36.1
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approachin a multisite test mode,presents with and without
screening approaches respectively, and compares the two.
Simulation results are presented in Section 5. Finally Sec-
tion 6 concludes the paper.
2. Problem Definition
This paper deals with test approaches which employ differ-
ent multisite techniques on an ATE with
allelism through multisite is used to simultaneously test
DUTs. This process is dependent on many parameters;
these parameters are either DUT or test process dependent.
DUT dependent parameters include yield, cardinality of the
test set, averagenumberof faults per DUT and expectedtest
outcome times (i.e. time to pass or fail the test). Parameters
which are test process dependent,are for examplefault cov-
erage,numberofchannelsandtouchdowntimeforthehead.
Four different approaches are considered in this paper:
? channels. Par-
?
1. ATEwithimmediatereplacement(idealcase): aDUT
which is found faulty by the ATE, is immediately re-
placedwith a new DUT (of unknownstatus). No time
overhead is associated with the replacement.
2. ATE with delayed replacement (realistic case): this
approach takes into account that DUTs which have
been found faulty by the ATE, cannot be replaced
while testing of the other DUTs takes place. Replace-
ment of faulty DUTs is delayed due to the constraint
in the operation of the head of the ATE.
3. Hybridwithscreening: BIST isexecutedfirst toreach
an intermediate fault coverage. DUTs which have
beenfoundfaultybytheBISTbasedprocessarepurged
(i.e. removed from the channels in the head) by de-
layed replacement. ATE based process is pursued
only for those DUTs which have passed the BIST
based test; these chips are reloaded on the ATE.
4. Hybrid with no screening: All chips undergo BIST
andATE based tests; at completionof the BIST based
test, DUTs which have been found faulty are still left
on the head. Reloading of the ATE is therefore not
required.
The objective is to fully characterize these approaches.
Newanalyticalmodelsareproposed. Touchdownandreload-
ing times are analyzed within these models. Hereafter, the
following assumptions are valid through the analysis.
1. DUTs are equal, i.e. an homogeneous batch is as-
sumed.
2. Each DUT is assigned a channel in the operation of
the head of the ATE.
3. A single head is assumed in the ATE architecture.
4. All channels of the ATE operate at the same speed.
3. Basic Characterization
This section deals with the characterization of test time in a
multisite tester with
parameters such as the fail time, the pass time, and yield of
a DUT.
? channels by incorporating different
3.1. Immediate Replacement
Consider initially the simplest case. The expected test time
of a DUT on a one-channel (serial) tester is given by
???????????????
(1)
where
?istheyield(inpercentage),and
is the test time by which the DUT passes the test process
(time to establish fault free status).
pected fail time for a DUT (time to detect a faulty DUT).
The expected test time for a DUT on a multisite tester
with
?
?(orpasstime)
?
?is defined as the ex-
? channels is a functionof the numberof channels,i.e.
?
The above expression assumes that when a DUT among
the set of
tected to be faulty, then it is immediately replaced, i.e. its
channelis allocatedtoanewDUTofunknownstatus. Hence,
?
?
?
?
????????????????
(2)
? DUTs (loaded on the head of an ATE) is de-
?
ment. However, this condition is not applicable in practice
[9] [10]. Specifically, as long as the test process for all
?is the DUT expected test time with immediate replace-
? DUTs is ongoing, individual faulty DUTs cannot be re-
placed, and the channel corresponding to each faulty DUT
remains idle till all DUTs in the set are tested. This oc-
curs due to the limitations incurred in the operation of the
head for the touchdown process and the inability to replace
chips without incurring in an alignment (and possibly a cal-
ibration of the equipment). Idle time periods are therefore
present and unavoidable in a multisite ATE. The idle time
period is a function of fail time and pass time of DUTs.
3.2. Delayed Replacement
This section considers the realistic scenario of delayed re-
placement and its impact on the test time of a multisite
tester. The probability of all DUTs in a set to be faulty is
, while the probability of at least one DUT to pass
the test and be identified as fault free is
If all
is actually
test time is given by
is
?????
?
???????
?
.
? DUTs have failed the test process, the test time
?
?. If number of failed DUTS is less than
?, the
?
?. So, the average test time for a DUT
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0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0
1000
2000
3000
4000
5000
6000
7000
8000
9000
10000
Yield
Idle Time (ms)
Pass Time = 2000mS
Fail Time = 200mS
C=8
C=4
C=2
C=1
Fig. 1. Idle time versus yield
??
?
?
?
?
???????
?
??
?
?????????
?
???
?
?(3)
Therefore, on average the idle time per channel is given
by the difference between ideal and realistic multisite test
time which is
?????
???????????????
?
??
?????????
(4)
So the average total idle time on a ATE with
can be expressed as
? channels
?
??
?
?
?
?
????
?
?
???????????????
?
??
?
???
?
??
?
?
(5)
Figure1 shows idletime versusyield(for
?????????
and
creases, the idle time increases too up to a maximum value
that is yield dependent.
The yield at which the maximum total idle time occurs,
can be obtained by differentiating the above equation and
solving it for
????????) under different values of
?; as
? in-
?, so
????????
?
?
??
??
?
(6)
This shows that as the number of channels
the yield at which the maximum total idle time occurs, de-
creases, thus implying that there is a relationship by which
the complexity of an ATE (as measured by
the manufacturing quality of the DUTs (as identified by the
yield). Moreover, it shows that the efficient utilization of
? increases,
?) depends on
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Yield
Scaled Test Time
1 Channel
2 Channels
4 Channels
8 Channels
ATE only (Delayed replacement) ATE only (Immediate replacement)
Fig. 2. Multisite ATE: scaled test time versus yield for dif-
ferent numbers of channels under delayed and immediate
replacement of DUTs
the channels is related to the yield of the DUTs, thus lim-
iting multisite testing to technologies which are inherently
stable (and thus with high yield).
For
cases (immediate and delayed replacements) are the same,
?
??, the test times under the ideal and realistic
??
?
?
?
?. Figure 2 shows the scaled test time ratio, i.e.
scaled test time is, the worst is the performance of a mutli-
site tester. In this figure, it is assumed
??
?
?
??
??
??
? for different values of
?. Higher the
?
?
??????and
?
under immediate and delayed replacements due to the pres-
ence of periods of idle time. For the two extreme cases of
yield (for values of 0 and 1) there is no difference in scaled
test time. However for yield values between 30% and 60%,
there is a considerable difference; for example, for a mul-
tisite tester with
12.5% of the time of a serial tester (
yield is 10%, the actual test time is about 40% of the serial
case.
?=
??????. There is a substantial difference in test time
?
??, the expected (ideal) test time is
?
??). However, if
3.3. Estimating Pass and Fail Times
To fully test a DUT, the complete test set (given by
tors) must be applied. The pass time
to thenumberoftestvectors:
analysis, we have assumed different vectors have same ap-
plication time. Consider next the expected fail time. If in a
DUT there is only one fault present among all faults (whose
number is given by
be detected as faulty by a vector
vectors in the test set is proportional to
? vec-
??is then proportional
???
? . Hereforsimplicityof
? ), then the probability of the DUT to
? among the
? available
?
?, i.e. regardless of
?. The fail time for a DUT is then proportionalto
? because
Paper 36.1
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none of the previous vectors (i.e. vectors numbered 1 up to
?
??) can detect the fault. The fail time is then given by
???
?
?
?
?
?
?
?
?
?
?
?
?
?
??
?
Let the possible averagenumberof faults per faultychip
be
to be detected faulty by a vector
vectors) is given by
?? (as discussed in [16]). So, the probability of a DUT
? (among the
? available
?
?
?
?
?
?
?
???
??
?
??
?
?
?
?
?
?
??
?
??
(7)
The fail time for a faulty chip with
given by
?? faults, is then
?
?
?
?
?
?
?
?
?
?
?
?
?
?
???
??
??
?
?
?
?
??
?
??
?
?
?
?
??
?? (8)
We notice that the application of a vector may detect
more than one fault. In the above analysis, it is implicitly
assumed that each fault is detected by only one vector. This
assumption is pessimistic (or safer) and allows to identify
an upper bound on the fail time, i.e. it allows to consider
the longest fail time (or the shortest idle time period) when
analyzing the performanceof a multisite tester. We use ’fail
time’ to refer to ’maximum fail time’ throughout the paper.
Figure 3 shows the ratio of
tical axis versus the number of test vectors on the horizon-
tal axis for different numbers of faults in a faulty DUT. As
shown the fail and pass times are a function of the average
number of faults per chip and the number of vectors in the
test set (as measure of the testability of a DUT); this analy-
sis shows that as a probabilistic approximation,the fail time
is
??to
??(i.e.,
??
??) on the ver-
?
?
??
?times the pass time.
4. Hybrid Approach
In this paper, testing is considered as a series of stages, at
each stage a procedurewhich involves a piece of equipment
andtestalgorithmisused. Thischaracterizationisamenable
to current testing practice in which chips go through dif-
ferent steps such as gross test (probing or wafer sorting),
boolean test (after packaging) and finally parametric test
[1].
Yield must be considered at each stage of this process.
The wafer yield is at the input of the first stage, the gross
yield is at the input of the booleantest stage which in turn is
the output of the gross test stage. The booleanyield is at the
beginningof the parametric test stage which in turn is at the
output of the boolean test. This three-stage model is shown
in Figure 4.
0
20
40
60
80
100
120
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Fail Time/PassTime
# of Vectors
n 0 =1
n 0 =3
n 0 =7
n 0 =9
Fig. 3.
numbers of faults per faulty DUT
??
??
versus number of vectors for different average
Consider the boolean test stage as applicable to this pa-
per. Two schemes for hybrid multisite testing are possible,
namely BIST/ATE with and without screening. In the first
case, BIST is performed on all DUTs until an intermediate
level of fault coverageis achieved. ATE is thenutilized only
on those DUTs which have successfully passed the BIST
stage. Basically, BIST is used to screen faulty DUTs, hence
the name of the approach. Since the defect level among
DUTs submitted to the ATE based process is lower, an en-
hancement in yield is expected for the hybrid process so the
idle time should be reduced.
In the second scheme, BIST is performed on the DUTs
inparalleltillanintermediateleveloffaultcoverageis achieved.
After BIST, an ATE based test is performed. Tests are ap-
plied to the DUTs and no screening is employed by using
BIST (faulty chips are not purgedor removedfromthe head
of the ATE).
Thehybridschemewithscreeninginvolvesanadditional
touchdown time because we have to reload the head with
those DUTs which have passed the BIST test stage. The
second scheme (no screening) does not require this addi-
tional touchdown and benefits only from the reduced differ-
ence between fail and pass times.
Before presenting in detail the proposed schemes, the
BIST and ATE pass and fail times must be analyzed. Let
?
approach. In BIST, the status of each DUT is not known
until all BIST vectors are applied. So
(negligible idle time is present for BIST).
to achieve intermediate BIST coverage
coverage at which testing is switched from BIST to ATE
and is based on the model presented in [8]. To determine
?
?(
??
?) be the BIST stage pass (fail) time in the hybrid
?
?
?is the same as
?
?
?
?
?
?is test time
??. This is the fault
?
?
?the fault coverage and its changes as a function of the
Paper 36.1
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Wafer Gross TestBoolean TestParametric Test
FailFailFail
PassPassPass
Wafer
Yield
Gross
Yield
Boolean
Yield
Fig. 4. Test model (three stages)
number of random test patterns must be analyzed [4] [5]
[21]. For simplicity of analysis we used the model from [4].
In this model, the BIST fault coverage after applying the
?th vector is given by
?
?
?
?
?????
?
?
?????
?
??
?
(9)
where
?
?is the required final fault coverage (as per the
specified defect level) and
to model the random-resilience of faults. The larger
the easier the faults are detected by random patterns.
Astest timeisproportionaltothenumberoftestvectors,
then it is possible to solve for
for BIST, i.e.
? denotes a constant that is used
? is,
?and to find the pass time
??
?
???
?
?
?
??
??
??
?
?
??
?
(10)
Let
??
?(
??
?) be the ATE stage pass (fail) time in the
hybrid approach.
??
?is test time to achieve ATE coverage
?
ber of faults per faulty chip (
Therelationshipbetweenthefaultcoverageandthenum-
ber of deterministic patterns can be established using the
minimal test sets given in [19] [20] and verified by fault
simulation for the ISCAS benchmark circuits (both combi-
national and full-scan versions of the sequential circuits). It
has been shown [8] that on a semi-logarithmic scale the re-
lationship between test set size and fault coverage is almost
linear. As per this empirical observation, the fault coverage
can be estimated as a function of the number of determinis-
tic test patterns, i.e.
??
?
? and
??
?is definedbyconsideringtheaveragenum-
?
?) as outlined in Section 3.
??
?
?
??
?
?
???
?
?
??
?
???
?
?
?
?
?
?
(11)
where
?
?is the number of patterns in the minimal test
set which are applied by the ATE and
first vector. Let
ATE [5] [8]. Based on this estimate, it is possible to solve
for
?
? is coverage of the
? denote the relative speed of BIST over
?and multiply the result by
? to obtain
?
?
?
?
?
???
?
?
?
?
?
?
?
?
?
?
????
?
???
(12)
4.1. Hybrid BIST/ATE with screening
In this section, the testing process of the boolean stage is
considered in more detail. Hybrid testing is considered as
made of two stages: (1) BIST and (2) ATE. All DUTs are
tested in the BIST test stage till the intermediate fault cov-
erage
be faulty and are purgedfromfurther testing (removedfrom
thehead). OnlythoseDUTswhichhavesuccessfullypassed
BIST, are then tested using an ATE to complete the boolean
test stage up to the required final fault coverage. The fea-
tures and implications of this hybrid approach are:
?
? is achieved. A number of chips are detected to
?Due to its faster application time, the difference be-
tween expected fail and pass times in BIST is signif-
icantly less than in a traditional boolean test stage in
which only external test is utilized [5].
?The test pass probability among the DUTs submitted
to the ATE stage is high; this means that most of the
DUTs in this stage are much likely to be not faulty.
Therefore, idle time is reduced as in Figure 1.
?Much likely, the number of DUTs which are tested
in parallel in the BIST stage, is larger than the ATE
stage because BIST often requires a smaller number
of ATE pins due to its on-chip capabilities. A one
time cost of a new probe card is needed.
The main disadvantage of this hybrid approach is that
there is a time penalty associated with an additional touch-
down of the head as each DUT could be loaded twice on the
tester. To alleviate this problem, a possible arrangement is
to perform BIST during the gross test. Screening is there-
fore implemented using BIST. Consider the multisite test
time using the proposed screening technique. In this case,
test time consists of two terms:
1. The time for the BIST stage by which most faulty
DUTs are rejected (to reduce the number of faulty
chips submitted to the ATE stage), thus increasingthe
yield. This is accomplished by achieving an interme-
diate fault coverage of
??.
Paper 36.1
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